Pixel Detector for the Protein Crystallography Beamline at the SLS

Pixel Detector for the Protein Crystallography Beamline at the SLS PSI Ch. Brönnimann 1, E. Eikenberry 1, S. Kohout 1, B. Schmitt 1, C. Schulze 1, R. Baur 2 and R.Horisberger 2 1 Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen-PSI 2 CMS-Project, Paul Scherrer Institut, CH-5232 Villigen-PSI University of Bonn P. Fischer 3, S. Florin 3 and M. Lindner 3 3 Physikalisches Institut der Universität Bonn, Nussallee 12 D-53115 Bonn

Data collection in protein crystallography Spot size: - Beam divergence - Mosaicity of the crystal - Distance sample-detector - Point spread function of detector Diffracted beam θ X-ray Detector Diffraction pattern Crystal rotation - 30-180 degree for complete data set - Currently: Discrete rotation, integration over certain rotation angle - Future: Continuous rotation, integration determined by detector frame rate ( Fine phi slicing) Crystallized Protein Resolution: 2d sin( θ ) = λ For d=1a and λ=1a, θ=60 o Beam Beam Energy: 5-17.5 13 kev Intensity: ~10 /s Focal spot size: 2 Adjustable to 25 x 15 µ m Divergency:150 µrad x 28 µrad (FWHM) Diffraction data - reflect crystal symmetry group - orientation of the crystal-> 4 orientation matrix - High dynamic range: >10 between strong and weak reflections - Intensities need to be determined accurately (1%) - Determination of amplitudes and phases leads to electron density maps Detector requirements: 2 - Large area (40 x 40 cm) and/or large number of pixels - Detect a high number of reflection orders (>500) - Accurate determination of integrated intensities - Wide dynamic range (>16 bit, i.e. single photon counting detector) - Fast readout (<0.1s)

Pixel Detectors: Principle Si pn-junction Al X-rays 3.6 ev to create 1 eh-pair p+ n+ E drift - + V bias n++ Detector 0.2 mm Pixel Sensor X-rays 0.3 mm 0.2 mm Sensor Pixel Read-out Chip Radiation hard Chip Bump Bonds Pixel electronics Bump Pad Cal Treshold correction CS Amp 1.7fF Global Tresh - Comp + Enable/ Disable Analog Block Ext/Comp Clock Ext Clock Φ 12 Clock Gen Digital Block 15 bit SR counter Reset RBI RBO

The SLS Pixel Detector & Size: 40 x 40 cm 2 (0.16m 2 ) & 2000 x 2000 pixels & Pixel size: 200 x 200 µm 2 & Modular detector -> dead area ~6% & High frame rate: >10Hz & High duty cycle: <6% (T ro ~6ms) & In operation: 1.8.2001 (1000x1000) Base plate (water cooled) Bank with 5 modules Modules with 16 chips

SLS Pixel Module Sensor Wire bonds Read-out chips High density flexible capton interconnect Base plate Al support Module Control Board MCB Cable

Module Geometry 2 4 6 8 10 12 14 16 0.11 9.82 18.25 1 3 5 7 9 11 13 15 36.5 35.4 34 0.18 79.6 81.0 Sensitive Area Horizontal Vertical Total Pixel size 0.2 0.2 mm 0.04 mm^2 Chip Nr of pixels 48 85 4080 Chip size 9.82 18.25 mm 179.215 mm^2 Sensor Nr of Pixels 398 170 67660 Nr of double pixels 14 170 2380 Sensor active area 79.6 34 2706.4 Module outside dim 81 36.6 mm 2964.6 mm^2 Sensor Pixels Readout chip Readout chip 200 110 Readout chip Readout chip 275 125 140 Chip Pixels

Main parameters Read-out electronics! Low noise analog block (ENC tot < 100 e-)! Shaping time t sh = 100 ns -> 1MHz! Radiation tolerant! power consumption <100 µw/pixel! Robust comparator! Individual threshold adjustment! Low overall threshold variation (σ < 100e-)! 15 bit pseudo random counter! Large size (20 x 10 mm 2 ) Prototypes Name Size Pixel Architecture Chip Subm. Receiv. Architecture SLS01 8x2 array Analog, comparator, - Dez 98 April 99 counter SLS02 22 x 30 Analog, comparator!, Indiv. May 99 Nov 99 counter, trimbits Coloumn architectur SLS03 1 x 90 As SLS02, final length - Aug 99 Mar 00 column SLS04 22 x 30 As SLS02 but with As SLS02 Dez 99 Exp May 00 correct comparator SLS05 30 x 30 As SLS04, improved trimbit mechanism SLS06 (Final chip) Indiv. Pixel Architecture (Yield tolerant design) Feb 00 Exp July 00 48 x 85 As SLS05 As SLS05 Exp Oct 00 Exp Feb 01

Pixel Layout Designed in radiation hard DMILL technology (R. Baur, Ch. Brönnimann) Size: 200 x 200 µm 2 Bump Pad 15 bit semi-static pseudo random counter+ control logic Low noise preamp (folded cascode) Shaper Threshold trimming (3 Bits) AC-coupled comparator Size 200 x 200 µm

SLS02 Architecture 15Bit Counter Column1 Pixel 30 Analog Vcal 1.5f 200f Pad Pr comp clk 10f Mode Icomp 20f 200f 100f Sh Phi1 Clockgen Comp LS + Dis Pixel Column22 DIS Mode Phi2 Pixel1 previous Xor ds_shift ds_shift ds_shift ds_shift ds_shift ds_shift Bit1 Bit2 Bit3 Bit13 Bit14 Bit15 next Xor CLK OUT CLK Mode Column Control Mode Column Column & & > Control & & > Control & & > In CLK Shift Shift Shift Clock Gen Clock Gen DOUT Clock Gen DIS ChipControl Shift FF Shift Clock gen TBI TCL TBO OUT

Pixel: Preamp-Shaper I =I +I comp c trim Vcal 1.7f 10f 20f Preamp Shaper Comp 80f 200f FB 100f FC=folded cascode SF=source follower FB=Feedback FC SF Preamp Shaper t peak ~30ns t ~60ns shape

SLS02 Analog Part Results Calibration signal Analog out signal! Noise measurements (without detector):! Amplification: ~60mV/1000e- 100ns/div, Ch1: 100mV/div, Ch2: 50mV/div! Linearity limit: ~6000e (21keV) ENC ~50e- (P=75 µw/pixel, t sh = 100 ns) Analog Output [mv] Noise depence on feedback resistors settings VRF\VRFS -700-600 -500-400 -300-200 300 96 71 63 74 45 70 200 95 69 61 56 50 77 100 96 82 67 75 64 78 0 120 98 100 75 83 100 450 400 350 300 250 200 150 100 50 y = 0.0564x + 18.14 0 0 1000 2000 3000 4000 5000 6000 7000 Signal charge 120 100 80 60 40 20 100-120 80-100 60-80 40-60 20-40 0-20 0-700 -600-500 -400-300 -200 300 100

Pixel: Comparator and trimming AC-coupled comparator with diode feedback simple inverter as comparator comparator biasing done via pn-junction of the diode -> expect lower threshold variations on the chip radiation insensitive low power consumption local Threshold setting global Comp Level shift T1 T2 T3 Dis 100f I=5 b µ A Outc Vtrim Inc I~1 c0 µ A I~0.2 c µ A

Comparator Results! Minimum Threshold < 700e -! Threshold variation: 130 e- untrimmed Trimbits SLS04 Threshold trimming: Very low trim currents 1200 1100 1000 900 800 700 600 500 400 300 200 100 DVthr [e] Trim1 Trim2 Trim4 Trim7 Power 4.4 4.35 4.3 4.25 Vtrim [V] 4.2 4.15 0 4.1

SLS03: 2cm long column biased via periphery 90 18 1 supplies 1. supply in [V] out [V] [V] VD+ 5.025 4.81-0.22 VD- 0.000 0.22 +0.22 VA+ 5.024 4.93-0.09 VA- 0.000 0.10 +0.10 VSF- 1.012 1.14 +0.13 VC- 2.983 3.06 +0.08 VGND 3.741 3.50-0.24 Vsh 3.741 3.74 ±0.00 Vg+ 5.024 4.92-0.10 VC+ 5.024 4.95-0.07 160 140 Amplitude [mv] AOUT of Pixel #18 and #90 120 100 80 60 40 20 0-20 Pixel 18 Pixel 90 time [ns] -40-200 0 200 400 600 800 1000 1200 1400

SLS05 Architecture RTIN RΦ1 RΦ2 Row Control Shift Shift Shift Shift Shift Shift Column Control Cal In Clk CS Dis & & > RS&CS & Aout + RS&CS LS { Dis 0: Readout 1: Count In Xor Comp clk + comp 200f XOR VC- 30f Vrfs Sh 200f Clockgen Phi2 10f Vrf Phi1 Pr shift shift shift shift shift Bit1 Bit2 Bit3 Bit4 Bit5 shift shift shift Bit15 Bit14 Bit13 1.5f 100f Pad 15-bit counter Vcomp Pixel Trim bit 1 Trim bit 2 PSEL DIN 1: CS active 0: Selected pixel in cnt mode RTOUT CHSEL Shift CTOUT DCLK EN PSEL CAL Chip Control FF VA- CHSEL Shift Shift CTOUT & VD+ CTIN CHSEL CΦ1 CΦ2 CTOUT DOUT AOUT CHSEL PSEL

Final Chip: Yield estimation Yield measurements of SLS02 chip (22x30 pixels): Defects due to dynamic logic (Semi-static SR in Pixels): 3.8x10-4 /bit -> 5.8x10-3 /pixel (Yield for 85 pixel column: 60%) Defects in analog part: 3/19=0.842/chip Yield estimation for 48 x 85 pixel chip XY-Adressing, 133 SR-cells: 0.898 Analog part 0.346 30 bad pixels 0.916 Expected overall yield 0.28 Binomial Distribution 1.000E+00 Probability 8.000E-01 6.000E-01 4.000E-01 2.000E-01 Sum 0.000E+00 4045 4050 4055 4060 4065 4070 4075 4080 4085 Nr of Pixels working

Design of a large read-out chip for protein crystallography: Conclusions Prototype chips with 22x30 pixels are working Simulated final chip with one 20mm long column-> working Dynamic logic in DMILL is a yield killer Design with yield tolerant architecture is a must