NSBC114EDP6T5G Series. Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network

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Preferred Devices Dual Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device and its external resistor bias network. The digital transistor contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a baseemitter resistor. The digital transistor eliminates these individual components by integrating them into a single device. The use of a digital transistor can reduce both system cost and board space. The device is housed in the SOT963 package which is designed for low power surface mount applications. Features Simplifies Circuit Design Reduces Board Space Reduces Component Count The SOT963 Package can be Soldered using Wave or Reflow. Available in 4 mm, 00 Unit Tape & Reel These are PbFree Devices These are HalideFree Devices MAXIMUM RATINGS (T A = 25 C unless otherwise noted) Rating Symbol Value Unit Collector-Base Voltage V CBO 50 Vdc Collector-Emitter Voltage V CEO 50 Vdc Collector Current I C 0 madc Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. (3) Q 1 NPN SILICON DIGITAL TRANSISTORS R 2 R 1 (2) R 1 R 2 (1) Q 2 (4) (5) (6) SOT963 CASE 527AD X M MARKING DIAGRAM 1 XM = Specific Device Code = Date Code = PbFree Package ORDERING INFORMATION Device Package Shipping SOT963 (PbFree) 00 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD11/D. DEVICE MARKING INFORMATION See specific marking information in the device marking table on page 2 of this data sheet. Semiconductor Components Industries, LLC, 2008 October, 2008 Rev. 3 1 Publication Order Number: NSBC114EDP6/D

THERMAL CHARACTERISTICS SINGLE HEATED Characteristic Symbol Max Unit T A = 25 C (Note 1) Thermal Resistance (Note 1) Junction-to-Ambient 231 1.9 R JA 540 C/W T A = 25 C (Note 2) 269 2.2 Thermal Resistance (Note 2) Junction-to-Ambient R JA 464 C/W DUAL HEATED (Note 3) T A = 25 C (Note 1) Thermal Resistance (Note 1) Junction-to-Ambient 339 2.7 R JA 369 C/W T A = 25 C (Note 2) 408 3.3 Thermal Resistance (Note 2) Junction-to-Ambient R JA 306 C/W Junction and Storage Temperature T J, T stg 55 to +150 C 1. FR4 @ 0 mm 2, 1 oz. copper traces, still air. 2. FR4 @ 500 mm 2, 1 oz. copper traces, still air. 3. Dual heated values assume total power is sum of two equally powered channels. DEVICE MARKING AND RESISTOR VALUES Device Marking* R1 (k) R2 (k) Package Shipping A (270 ) NSBC124EDP6T5G R (0 ) 22 22 NSBC144EDP6T5G D (0 ) 47 47 P (0 ) 47 NSBC123TDP6T5G A (90 ) 2.2 T (0 ) 4.7 4.7 Y (0 ) 4.7 47 D (90 ) 2.2 47 V (0 ) 47 22 NSBC114TDP6T5G R (1 ) F (0 ) 0 SOT963 (PbFree) 00/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD11/D. *(XX ) = Degree rotation in the clockwise direction. 2

ELECTRICAL CHARACTERISTICS (T A = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS CollectorBase Cutoff Current (V CB = 50 V, I E = 0) I CBO 0 nadc CollectorEmitter Cutoff Current (V CE = 50 V, I B = 0) I CEO 500 nadc EmitterBase Cutoff Current (V EB = 6.0 V, I C = 0) NSBC124EDP6T5G NSBC144EDP6T5G NSBC114TDP6T5G NSBC123TDP6T5G CollectorBase Breakdown Voltage (I C = A, I E = 0) V (BR)CBO 50 Vdc CollectorEmitter Breakdown Voltage (Note 4) (I C = 2.0 ma, I B = 0) I EBO 0.5 0.1 0.9 4.0 0.1 1.5 0.18 0. madc V (BR)CEO 50 Vdc ON CHARACTERISTICS (Note 4) DC Current Gain (V CE = V, I C = 5.0 ma) NSBC124EDP6T5G NSBC144EDP6T5G NSBC114TDP6T5G//NSBC123TDP6T5G CollectorEmitter Saturation Voltage (I C = ma, I B = 0.3 ma) /NSBC124EDP6T5G NSBC144EDP6T5G/ / (I C = ma, I B = 1 ma) / NSBC114TDP6T5G/NSBC123TDP6T5G (I C = ma, I B = 5.0 ma) h FE 35 60 160 15 60 0 140 140 350 30 200 150 140 V CE(sat) 5 Vdc Output Voltage (on) (V CC = 5.0 V, V B = 2.5 V, R L = k ) NSBC114TDP6T5G NSBC124EDP6T5G NSBC123TDP6T5G (V CC = 5.0 V, V B = 3.5 V, R L = k ) NSBC144EDP6T5G (V CC = 5.0 V, V B = 4.0 V, R L = k ) (V CC = 5.0 V, V B = 5.0 V, R L = k ) V OL Vdc 4. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%. 3

ELECTRICAL CHARACTERISTICS (T A = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit ON CHARACTERISTICS (Note 5) Characteristic Symbol Min Typ Max Unit Output Voltage (off) (V CC = 5.0 V, V B = 0.5 V, R L = k ) /NSBC124EDP6T5G NSBC144EDP6T5G/ / (V CC = 5.0 V, V B = 5 V, R L = k ) NSBC123TDP6T5G//NSBC114TDP6T5G/ Input Resistor NSBC114TDP6T5G NSBC124EDP6T5G NSBC144EDP6T5G NSBC123TDP6T5G NSBC144WDP6TG Resistor Ratio /NSBC124EDP6T5G/ NSBC144EDP6T5G/NSBC123EDP6T5G NSBC114TDP6T5G///NSBC123TDP6T5G 5. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%. V OH 4.9 Vdc R1 7.0 7.0 15.4 32.9 7.0 7.0 1.5 3.3 3.3 1.54 32.9 70 R 1 /R 2 0.8 0.17 0.055 0.038 1.7 22 47 2.2 4.7 4.7 2.2 47 0 1 0.1 0.047 2.1 28.6 61.1 2.9 6.1 6.1 2.86 61.1 0 1.2 5 0.185 0.056 2.6 k 4

TYPICAL ELECTRICAL CHARACTERISTICS V CE(SAT), COLLECTORTOEMITTER SATURATION VOLTAGE (V) C OBO, OUTPUT CAPACITANCE (pf) I C /I B = T A =25 C T A = 150 C 0. T A = 55 C 0.01 0 5 15 20 25 30 35 40 45 50 Figure 1. V CE(sat) vs. I C 2.40 2.20 2.00 1. 1.60 1.40 1.20 0 h FE, DC CURRENT GAIN 00 V CE = V 25 C 0 150 C 55 C 0.1 1 0 Figure 2. DC Current Gain 0 150 C 1 55 C 0.1 25 C 0. 0.01 0 5 15 20 25 30 35 40 45 50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V CB, COLLECTOR BASE VOLTAGE (V) V in, INPUT VOLTAGE (V) Figure 3. Output Capacitance Figure 4. Output Current vs. Input Voltage V in, INPUT VOLTAGE (V) 25 C 150 C 55 C 0. 0 5 15 20 25 30 35 40 45 50 Figure 5. Input Voltage vs. Output Current 5

TYPICAL APPLICATIONS FOR NPN BRTs +12 V ISOLATED LOAD FROM P OR OTHER LOGIC Figure 6. Level Shifter: Connects 12 or 24 Volt Circuits to Logic +12 V V CC OUT IN LOAD Figure 7. Open Collector Inverter: Inverts the Input Signal Figure 8. Inexpensive, Unregulated Current Source 6

PACKAGE DIMENSIONS SOT963 CASE 527AD01 ISSUE D D 6 5 4 1 2 3 e A B E 6X b 0.08 C A B C A C L H E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. MILLIMETERS DIM MIN NOM MAX A 0.34 0.37 0.40 b 0. 0.15 0 C 0.07 0.12 0.17 D 0.95 0 5 E 0.75 0. 0.85 e 0.35 BSC L 0.05 0. 0.15 H E 0.95 0 5 INCHES MIN NOM MAX 0.004 0.006 0.008 0.003 0.005 0.007 0.037 0.039 0.041 0.03 0.032 0.034 0.014 BSC 0.002 0.004 0.006 0.037 0.039 0.041 SOLDERING FOOTPRINT* 0.35 0.014 0.35 0.014 0.90 0.0354 0 0.008 0 0.008 SCALE 20:1 mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 217 USA Phone: 3036752175 or 03443860 Toll Free USA/Canada Fax: 3036752176 or 03443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 02829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 29 Japan Customer Focus Center Phone: 857733850 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NSBC114EDP6/D