March 13, 2006 Microchip PIC18F4320-I/ML Enhanced Flash Microcontroller Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 1.5 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Analysis 3.1 Package Overview 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors 4.7 Passives 4.8 Isolation 4.9 Wells and Substrate 5 Memory Blocks 5.1 SRAM 5.2 Flash Memory Rev. 1.0 Apr 30, 2004 SAR-0405-002
Structural Analysis 6 Selected Layout Features 6.1 Description 6.2 Redundant Vias 6.3 SRAM Array 6.4 Standard Cells 6.5 Other Memory Arrays 6.6 Analog Circuit 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions Report Evaluation Rev. 1.0 Apr 30, 2004 SAR-0405-002
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package Side-View 2.1.4 Plan-View Package X-Ray 2.1.5 Cross-Section Package X-Ray 2.1.6 Die Photograph 2.1.7 Annotated Die Photograph 2.1.8 Die Markings 2.1.9 Die Markings 2.2.1 Die Corner 2.2.2 Die Corner 2.2.3 Die Corner 2.2.4 Die Corner 2.2.5 Minimum Pitch Bond Pads 2.2.6 Detail of Typical Bond Pad 3 Package Analysis 3.1.1 Package Overview 3.1.2 Stitch Bond Land 3.1.3 Detail of Stitch Bond 3.1.4 Thermosonic Ball Bonds 3.1.5 Die Attach 3.1.6 Die Edge 4 Process Analysis 4.1.1 General Device Structure of PIC18F4320-I/ML 4.1.2 General Device Structure of PIC18F4320-I/ML 4.1.3 Die Edge 4.1.4 Seal Ring 4.2.1 Bond Pad in Plan View 4.2.2 Overall View of Bond Pad Structure 4.2.3 Detail of Bond Pad Structure 4.3.1 Final Device Passivation 4.3.2 IMD Structure Rev. 1.0 May 3, 2004 SAR-0405-002
Overview 1-2 4.3.3 Pre-Metal Dielectric 4.4.1 Minimum Pitch Metal 2 4.4.2 Minimum Pitch Metal 1 4.5.1 Vias and Contacts 4.5.2 Contacts to Polycide and Polysilicon 4.5.3 Minimum Pitch Contacts to N + Diffusion 4.5.4 Minimum Pitch Contacts to P + Diffusion 4.6.1 Minimum NMOS Gate 4.6.2 Minimum PMOS Gate 4.6.3 Oxide Etch of Gates 4.7.1 Double Poly Capacitor 4.7.2 Detail of Capacitor Stack 4.7.3 Polysilicon Resistors 4.8.1 Minimum Width Isolation 4.8.2 Birds Beak Profile 4.9.1 Optical Image of Wells 4.9.2 FESEM Image of Wells in SRAM 5 Memory Blocks 5.1.1 Plan View of 6T SRAM 5.2.1 Perspective View of Flash Memory Array 5.2.2 Plan View of Flash Memory Array 5.2.3 Cross-Section of Flash Array 6 Selected Layout Features 6.1.1 Annotated Die Photograph Metal 2 6.2.1 Power Line Redundant Vias Between M1 and M2 Metal 1 Photograph 6.2.2 Power Line Redundant Vias Between M1 and M2 Metal 2 Photograph 6.2.3 Signal Line Redundant Vias Between M1 and M2 Metal 1 Photograph 6.2.4 Signal Line Redundant Vias Between M1 and M2 Metal 2 Photograph 6.3.1 SRAM Array Metal 2 Photograph 6.3.2 SRAM Array Metal 2 Photograph Rev. 1.0 May 3, 2004 SAR-0405-002
Overview 1-3 6.3.3 SRAM Array Polycide Photograph 6.4.1 Typical Standard Cell Block Metal 2 Photograph 6.4.2 Typical Standard Cell Block Metal 2 Photograph 6.4.3 Standard Cell Polycide Photograph 6.4.4 Standard Cell Metal 1 Photograph 6.4.5 Standard Cell Metal 2 Photograph 6.5.1 Array 1 Polycide Photograph 6.5.2 Array 1 Metal 1 Photograph 6.5.3 Array 2 Polycide Photograph 6.6.1 Analog Circuit Polycide Photograph 6.6.2 MOS Capacitor Polycide Photograph 6.6.3 Long Channel MOS Transistor Polycide Photograph 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 1.2 List of Tables 4.3.1 Dielectric Thicknesses 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.6.1 Transistor and Polycide Dimensions Rev. 1.0 May 3, 2004 SAR-0405-002
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