IRFP60, SiHFP60 Power MOSFET PRODUCT SUMMRY (V) 500 R DS(on) (Ω) = 0 V 0.27 Q g (Max.) (nc) 05 Q gs (nc) 26 Q gd (nc) 2 Configuration Single TO-27 S G D ORDERING INFORMTION Package Lead (Pb)-free SnPb G D S N-Channel MOSFET FETURES Low Gate Charge Q g Results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and valanche Voltage and Current Effective C oss Specified Compliant to RoHS Directive 2002/95/EC PPLICTIONS Switch Mode Power Supply (SMPS) Uninterruptable Power Supply High Speed Power Switching TYPICL SMPS TOPOLOGIES Full Bridge PFC Boost TO-27 IRFP60PbF SiHFP60-E3 IRFP60 SiHFP60 vailable RoHS* COMPLINT BSOLUTE MXIMUM RTINGS T C = 25 C, unless otherwise noted PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage 500 V Gate-Source Voltage ± 30 Continuous Drain Current at 0 V T C = 25 C 20 T C = 00 C 3 Pulsed Drain Current a M 80 Linear Derating Factor 2.2 W/ C Single Pulse valanche Energy b E S 960 mj Repetitive valanche Current a I R 20 Repetitive valanche Energy a E R 28 mj Maximum Power Dissipation T C = 25 C P D 280 W Peak Diode Recovery dv/dt c dv/dt 3.8 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for 0 s 300 d C Mounting Torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L =.3 mh, R g = 25 Ω, I S = 20 (see fig. 2). c. I SD 20, di/dt 25 /µs, V DD, T J 50 C. d..6 mm from case. 0 lbf in. N m * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 923 www.vishay.com S09-28-Rev. B, 3-Jul-09
IRFP60, SiHFP60 THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 0 Case-to-Sink, Flat, Greased Surface R thcs 0.2 - C/W Maximum Junction-to-Case (Drain) R thjc - 0.5 SPECIFICTIONS T J = 25 C, unless otherwise noted PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage = 0 V, = 250 µ 500 - - V Temperature Coefficient Δ /T J Reference to 25 C, = m - 0.6 - V/ C Gate-Source Threshold Voltage (th) =, = 250 µ 2.0 -.0 V Gate-Source Leakage I GSS = ± 30 V - - ± 00 n = 500 V, = 0 V - - 25 Zero Gate Voltage Drain Current SS = 00 V, = 0 V, T J = 25 C - - 250 µ Drain-Source On-State Resistance R DS(on) = 0 V = 2 b - - 0.27 Ω Forward Transconductance g fs = 50 V, = 2 b - - S Dynamic Input Capacitance C iss = 0 V, - 300 - Output Capacitance C oss = 25 V, - 80 - f =.0 MHz, see fig. 5 Reverse Transfer Capacitance C rss - 8 - pf =.0 V, f =.0 MHz 30 Output Capacitance C oss = 0 V = 00 V, f =.0 MHz 30 Effective Output Capacitance C oss eff. = 0 V to 00 V c 0 Total Gate Charge Q g - - 05 Gate-Source Charge Q gs I = 0 V D = 20, = 00 V, see fig. 6 and 3 b - - 26 nc Gate-Drain Charge Q gd - - 2 Turn-On Delay Time t d(on) - 8 - Rise Time t r V DD = 250 V, = 20, - 55 - Turn-Off Delay Time t d(off) R G =.3 Ω, R D = 3 Ω, see fig. 0 b - 5 - ns Fall Time t f - 39 - Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S MOSFET symbol - - 20 D showing the integral reverse Pulsed Diode Forward Current a G I SM p - n junction diode - - 80 S Body Diode Voltage V SD T J = 25 C, I S = 20, = 0 V b - -.8 V Body Diode Reverse t rr - 80 70 ns Recovery Time T J = 25 C, I F = 20, di/dt = 00 /µs b Body Diode Reverse Recovery Charge Q rr - 5.0 7.5 µc Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 µs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while is rising from 0 % to 80 %. www.vishay.com Document Number: 923 2 S09-28-Rev. B, 3-Jul-09
IRFP60, SiHFP60 TYPICL CHRCTERISTICS 25 C, unless otherwise noted, Drain-to-Source Current () 923_0 0 2 0 Top 0. 0. Bottom 5 V 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V.5 V.5 V 20 µs Pulse Width T C = 25 C 0 0 2, Drain-to-Source Voltage (V), Drain-to-Source Current () 923_03 0 2 0 0..0 50 C 25 C 20 µs Pulse Width = 50 V 5.0 6.0 7.0 8.0 9.0, Gate-to-Source Voltage (V) Fig. - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics, Drain-to-Source Current () 923_02 0 2 0 Top Bottom 5 V 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V.5 V.5 V 20 µs Pulse Width T C = 50 C 0 0 2, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics R DS(on), Drain-to-Source On Resistance (Normalized) 923_0 3.0 2.5 2.0.5.0 0.5 = 20 = 0 V 0.0-60 - 0-20 0 20 0 60 80 00 20 0 60 T J, Junction Temperature ( C) Fig. - Normalized On-Resistance vs. Temperature Document Number: 923 www.vishay.com S09-28-Rev. B, 3-Jul-09 3
IRFP60, SiHFP60 Capacitance (pf) 923_05 0 5 0 0 3 0 2 0 0 = 0 V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd, Drain-to-Source Voltage (V) C iss C oss C rss 0 2 0 3 I SD, Reverse Drain Current () 923_07 0 2 50 C 0 25 C = 0 V 0. 0.2 0. 0.6 0.8.0.2..6 V SD, Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage, Gate-to-Source Voltage (V) 923_06 20 6 2 8 = 20 = 00 V = 250 V = 00 V For test circuit see figure 3 0 0 20 0 60 80 00 Q G, Total Gate Charge (nc), Drain Current () 923_08 0 3 0 2 0 Operation in this area limited by R DS(on) 0 µs 00 µs ms T C = 25 C T J = 50 C Single Pulse 0 ms 0 0 2 0 3 0, Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating rea www.vishay.com Document Number: 923 S09-28-Rev. B, 3-Jul-09
IRFP60, SiHFP60 R D 20 R G D.U.T. - V DD, Drain Current () 5 0 5 0 V Pulse width µs Duty factor 0. % Fig. 0a - Switching Time Test Circuit 90 % 923_09 0 25 50 75 00 25 50 T C, Case Temperature ( C) 0 % t d(on) t r t d(off) t f Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 0b - Switching Time Waveforms Thermal Response (Z thjc ) 923_ D = 0.5 0. 0.2 0. 0.05 0.02 0.0 0-2 0-3 Single Pulse (Thermal Response) 0-5 0-0 -3 0-2 0. t, Rectangular Pulse Duration (S) Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case P DM t t 2 Notes:. Duty Factor, D = t /t 2 2. Peak T j = P DM x Z thjc T C 5 V t p L Driver R G 20 V t p D.U.T. I S 0.0 Ω - V DD I S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms Document Number: 923 www.vishay.com S09-28-Rev. B, 3-Jul-09 5
IRFP60, SiHFP60 E S, Single Pulse valanche Energy (mj) 923_2c 200 2000 600 200 800 00 Top Bottom 8.9 3 20 0 25 50 75 00 25 50 Starting T J, Junction Temperature ( C) Fig. 2c - Maximum valanche Energy vs. Drain Current av, valanche Voltage (V) 923_2d 620 600 580 560 50 0 8 2 6 20 I V, valanche Current () Fig. 2d - Typical Drain-to-Source Voltage vs. valanche Current Current regulator Same type as D.U.T. 0 V Q G 2 V 0.2 µf 50 kω 0.3 µf Q GS Q GD D.U.T. V - DS V G Charge Fig. 3a - Basic Gate Charge Waveform 3 m Fig. 3b - Gate Charge Test Circuit I G Current sampling resistors www.vishay.com Document Number: 923 6 S09-28-Rev. B, 3-Jul-09
IRFP60, SiHFP60 Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period = 0 V* D.U.T. I SD waveform Reverse recovery current Re-applied voltage Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt Inductor current Body diode forward drop V DD Ripple 5 % I SD * = 5 V for logic level devices Fig. - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?923. Document Number: 923 www.vishay.com S09-28-Rev. B, 3-Jul-09 7
www.vishay.com TO-27C (High Voltage) Package Information 3 B R/2 Q E E/2 S 2 7 ØP (Datum B) Ø k M D B M ØP D2 2 x R (2) D D 2 3 D Thermal pad 5 L C 2 x b2 3 x b 0.0 M C M b Lead ssignments. Gate 2. Drain 3. Source. Drain 2 x e L See view B C DDE (b, b2, b) () Section C - C, D - D, E - E MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX..58 5.3 0.80 0.209 D2 0.5.30 0.020 0.05 2.2 2.59 0.087 0.02 E 5.29 5.87 0.602 0.625 2.7 2.9 0.06 0.098 E 3.72-0.50 - b 0.99.0 0.039 0.055 e 5.6 BSC 0.25 BSC b 0.99.35 0.039 0.053 Ø k 0.25 0.00 b2.53 2.39 0.060 0.09 L.20 6.25 0.559 0.60 b3.65 2.37 0.065 0.093 L 3.7.29 0.6 0.69 b 2.2 3.3 0.095 0.35 N 7.62 BSC 0.300 BSC b5 2.59 3.38 0.02 0.33 Ø P 3.5 3.66 0.38 0. c 0.38 0.86 0.05 0.03 Ø P - 7.39-0.29 c 0.38 0.76 0.05 0.030 Q 5.3 5.69 0.209 0.22 D 9.7 20.82 0.776 0.820 R.52 5.9 0.78 0.26 D 3.08-0.55 - S 5.5 BSC 0.27 BSC ECN: X3-003-Rev. D, 0-Jul-3 DWG: 597 Notes. Dimensioning and tolerancing per SME Y.5M-99. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions D and E. 5. Lead finish uncontrolled in L. 6. Ø P to have a maximum draft angle of.5 to the top of the part with a maximum hole diameter of 3.9 mm (0.5"). 7. Outline conforms to JEDEC outline TO-27 with exception of dimension c. 8. Xian and Mingxin actually photo. E View B C C Planting (c) E 0.0 M D B M View - (b, b3, b5) Base metal c Revision: 0-Jul-3 Document Number: 9360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?9000
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