Power MOSFET V,, Single N Channel, Features Low Package Inductance Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual Sided Cooling Capability Compatible with SQ Footprint and Outline This is a Pb Free Device pplications CPU Power Delivery DC DC Converters Optimized for both Synch FET and Control FET MXIMUM RTINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS ± V T = C I D. Current R J (Note ) T = 7 C. Power Dissipation R J (Note ) Current R J PCB (Note ) Power Dissipation R J PCB (Note ) Current R JC (Note ) Power Dissipation R JC (Note ) Steady State T = C P D. W T = C I D T = 7 C 6 T = C P D 6 W T C = C I D 66 T C = 7 C T C = C P D W Pulsed Drain Current T = C, t p = s I DM Current Limited by Package T = C I Dmax Operating Junction and Storage Temperature T J, T stg to C Source Current (Body Diode) (Note ) I S Drain to Source DV/DT dv/dt 6. V/ns Single Pulse Drain to Source valanche Energy (, V DD = V, V GS = V, I L =. pk, L =. mh, R G = ) Lead Temperature for Soldering Purposes (/ from case for s) E S mj T L 7 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surfacemounted on FR board using sq in pad, oz Cu.. Measured with a T J of approximately 9 C using oz Cu board. G V (BR)DSS R DS(ON) MX I D MX V ÍÍ B PD CSE D 6. m @ V 9. m @. V ORDERING INFORMTION Device Package Shipping NTMKB9NTG NTMKB9NTG (Pb Free) (Pb Free) MRKING DIGRM B9 YWW B9= Specific Device Code = ssembly Location Y = Year WW = Work Week = Pb Free Package (Note: Microdot may be in either location) D S N CHNNEL MOSFET /Tape & Reel /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: NTMKB9N/D
THERML RESISTNCE MXIMUM RTINGS Parameter Symbol Value Unit Junction to Case (Drain) (Note ) R JC. C/W Junction to mbient Steady State (Note ) R J Junction to PCB (Note ) R J PCB. ELECTRICL CHRCTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHRCTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = V Drain to Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current I DSS V GS = V, V DS = V V (BR)DSS /T J mv/ C. T J = C Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ± n ON CHRCTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D =.6. V Negative Threshold Temperature Coefficient V GS(TH) /T J.7 mv/ C Drain to Source On Resistance R DS(on) V GS = V, I D =. 6. m V GS =. V, I D = 7. 9. Forward Transconductance g FS V DS = V, I D = S CHRGES, CPCITNCES ND GTE RESISTNCE Input Capacitance C iss 6 pf Output Capacitance C oss VGS = V, f =. MHz, VDS = V Reverse Transfer Capacitance C rss Total Gate Charge Q G(TOT) Threshold Gate Charge Q G(TH). Gate to Source Charge Q GS V GS =. V, V DS = V, I D =. Gate to Drain Charge Q GD.6.9 nc Total Gate Charge Q G(TOT) V GS = V, V DS = V, I D = nc SWITCHING CHRCTERISTICS (Note ) Turn On Delay Time t d(on) Rise Time t r V GS =. V, V DS = V,.6 Turn Off Delay Time t d(off) I D =, R G =. 6. Fall Time t f. DRIN SOURCE DIODE CHRCTERISTICS Forward Diode Voltage V SD V GS = V, I S =. ns.. V T J = C.66 Reverse Recovery Time t RR.6 ns Charge Time t a V GS = V, d IS /d t = / s, 7. Discharge Time t b I S =. Reverse Recovery Charge Q RR. nc PCKGE PRSITIC VLUES Gate Resistance R G T = C.9.. Pulse Test: pulse width = s, duty cycle %.. Switching characteristics are independent of operating junction temperatures.
TYPICL CHRCTERISTICS 6 V 7. V... V. V...6 V. V. V. V. V.6 V. V. V. V. V DS V 6 T J = C T J = C.... V GS, GTE TO SOURCE VOLTGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRIN TO SOURCE RESISTNCE ( ).6.....9.7.6.. 6 V GS, GTE TO SOURCE VOLTGE (V) Figure. On Resistance vs. Gate to Source Voltage 7 I D = 9 R DS(on), DRIN TO SOURCE RESISTNCE (m )..9..7.6.... V GS =. V V GS = V Figure. On Resistance vs. Drain Current and Gate Voltage 6 7 R DS(on), DRIN TO SOURCE RESISTNCE (NORMLIZED).6.......9..7.6 I D = V GS = V 7 I DSS, LEKGE ().E.E 6.E 7.E.E 9.E V GS = V T J = C T J = C T J, JUNCTION TEMPERTURE ( C) Figure. On Resistance Variation with Temperature Figure 6. Drain to Source Leakage Current vs. Voltage
TYPICL CHRCTERISTICS C, CPCITNCE (pf) 6 6 C iss Q gs Q gd C oss C rss Figure 7. Capacitance Variation V GS = V V GS, GTE TO SOURCE VOLTGE (V) 9 7 6 QT Q g, TOTL GTE CHRGE (nc) V DD = V V GS = V I D = Figure. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = V I D = V GS =. V t d(off) t r t f t d(on) I S, SOURCE CURRENT () 6 V GS = V R G, GTE RESISTNCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V GS V Single Pulse T C = C. R DS(on) Limit Thermal Limit Package Limit.. Figure. Maximum Rated Forward Biased Safe Operating rea s s ms ms dc E S, SINGLE PULSE DRIN TO SOURCE VLNCHE ENERGY (mj). 9 7 6.....6.7..9 V SD, SOURCE TO DRIN VOLTGE (V) Figure. Diode Forward Voltage vs. Current I D =. 7 T J, STRTING JUNCTION TEMPERTURE( C) Figure. Maximum valanche Energy vs. Starting Junction Temperature.
PCKGE DIMENSIONS.x. B PD CSE D ISSUE O GTE PD REFERENCE. C. C NOTE. C E X D D F D ÍÍ TOP VIEW SIDE VIEW G D BOTTOM VIEW E. C E C E X SETING PLNE. X.9 SOLDERING FOOTPRINT*..6 NOTES:. DIMENSIONING ND TOLERNCING PER SME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS.. COPLNRITY PPLIES TO THE FLNGES OF LEDFRME ONLY. MILLIMETERS DIM MIN MX.6.6....7 D.7. D.. D.. D.. E.7.9 E.7. E.7.7 E.7.7 F.97 BSC G.7 BSC..9.9 X..6 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein, NTMKB9N, may be covered by U.S. Patents including 6,,. Other patents may be pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 6, Denver, Colorado 7 US Phone: 67 7 or 6 Toll Free US/Canada Fax: 67 76 or 67 Toll Free US/Canada Email: orderlit@onsemi.com N. merican Technical Support: 9 Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: 77 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTMKB9N/D