AGATA preamplifiers: issues and status Preamplifier group AGATA week Legnaro (Padova), Italy 15-19 September 2003 Speaker: Alberto Pullia, 16 September 2003
Work forces main developments Discrete hybrid solution (Milano, Koeln, GANIL, Padova,, GSI) Fully integrated solution (Saclay)
Introduction The group has met 3 times : Padova (September 2002) GSI (January 2003) Milano (May 2003) + here (17 September 2003)
Principal technical issues Low power dissipation of the FET + low noise Fast risetime Common calibration signal Fast de-saturation (after high-energy particle hits) PS and Active filtering of PS Controls and adjustments Pin out and size Specifications
Low power dissipation of FET s Plane 2: plugs Because of cooling requirements: cold finger <=30cm => Dewar content between 3 and 4 litres of LN 2! i.e.: reducing thermal losses and power!!! => i: FET power as low as possible (<25mW or even better? ) ii: cabling from plane 0/1 as long as possible to minimize thermal loss iii: number of cables from plane 0/1 per channel (it would be nice only two but in maximum three) Plane 1: feedthroughs Do not consider preamp philosophies which need more than three cables to support the cold stage of the preamp! Plane 0: cold FETs
Test of FET s @ low power (low V d ) BF862 or IF1331 Vd=1.7V Id=9mA (14mW) energy 122 kev 1.3 MeV resolution 0.96 kev fwhm 1.94 kev fwhm
Risetime: : limiting effects (I) 2nd stage amplification, stability/bandwidth bandwidth 2 nd stage amplification Stability/bandwidth we are confident to stay in this region
Risetime: : limiting effects (II) Fast pulser + diff. driver + 20m cable + receiver cables and drivers 12 ns risetime! Effect of 20m twisted-pair cable (with 100 Ohm termination). Can be compensated if necessary γ rays + MARS det + PA3.2 + diff. driver + 5m cable * + receiver * 5m twisted pair lvds cable and micro-delta-ribbon connectors (AMP)
Common test signal (old idea of M. Meyer) HV 1) pulser signal is injected onto HV electrode through the source of input FET a Pulser a 47 Ω 2.5 Ω 2) the pulser signal reaches all segments through their bulk capacitances Useful for calibration of inner segments in the low-energy region!
signals seen on segments Pulser line 60 Co lines
Saturation (after high-energy particles hit) Talk given by R. Saitoh at 2 nd preamp. group meeting (GSI, Jan 2003)
Saturation of charge loop λ (rate of 50 MeV particles) 1 khz (segments?) 10 khz (core?) R F (feedback resistor) 0.3 GΩG 0.5 GΩG 1 GΩG 0.3 GΩG 0.5 GΩG 1 GΩG V (dc voltage) 0.83 V 1.38 V 2.76 V 8.3 V 13.8 V 27.6 V V = 50 2.9 MeV ev/pair q C F C F RFλ Use 0.3 GΩG for core and ±12 V power supply!
New! Fast de-saturation of 2 nd stage Cold part of preamplifier 1st stage Warm part of preamplifier (typical) 2nd stage Output From detector Charge loop Passive P/Z Amplification New add-on de-saturation circuitry Capacitance to be discharged to de-saturate 2nd stage Discharge current Schmitt trigger comparator From ADC OVR 18 mm 38 mm
Fast de-saturation some results Amplitude [V] 4 3 2 1 2 3 4 5 6 7 8 10 9 11 Response of preamplifier: Curves (1)-(10) (10) = from 5 to 50 MeV Curve (11) = 100 MeV 1 0 0 2 4 6 8 10 12 Time [µs] ~7us to reset 50MeV event Linearity of TOT (Time Over Threshold) measurement Time over threshold [µs] 8 7 6 5 4 3 2 Measurement Linear fitting 1.0 1.5 2.0 2.5 3.0 3.5 0.8 0.6 0.4 0.2 0-0.2-0.4-0.6 Relative error [%] Test signal amplitude [V]
Active filters of power supplies +V PS in +V PS out CLC filters on main board enable On preamplifier board On preamplifier board enable -V PS in -V PS out More effective and compact than passive solutions 0.7 V voltage drop on either PS side
Control of gain and switch off Gain tolerance = 10% due mainly to parasitics of the feedback components & their soldering: gain equalization will be made digitally. Switch off of individual preamplifiers needed only for troubleshooting => jumpers
Adjustments Trimmer for P/Z adjustment (not strictly needed if digital P/Z is made effectively) Gain ranges : 1) 0-50 5 MeV, 2) 0-200 MeV remotely controlled in the FADC module Offset adjustment: remotely controlled with DAC s in the FADC module.
Pin out and size The boards will have a connector on either side. The idea of triples is gaining consensus. Max size of one preamplifier (either a single or 1/3 of a triple) is 22 mm x 48 mm.. Clearance in the transversal direction is 7 mm. Miniaturized, two-row connectors (18/20 vias) are being considered
Specifications Property value tolerance Conversion gain Noise Noise slope Rise time Rise-time slope Decay time Integral non linearity Output polarity Power supply Power consumption of input FET Power consumption (except diff. buffer) Mechanical dimension 100 mv / MeV (terminated) 0.6 kev fwhm (0 pf) 12±2 2 ev / pf 10 ns ± 2 ns (0 pf) ~0.3 ns / pf 50 us < 0.025% ( =3.5V( unterminated) Differential, Z=100Ω ±6V, ±12V < 25 mw < 250 mw < 22mm x 48 mm x 7 mm ±10% ±5 5 %
Block schemes & components Segment preamp From det FET <25mW Folded cascode PNP buff 2 nd stage with P/Z, amplification, diff buff Fast reset (optional) ADC OVR Core preamp From det Test input Folded cascode FET <25mW NPN buff Fast reset (optional) 2 nd stage with P/Z, amplification, diff buff ADC OVR Input FET NPN BJT s PNP BJT s BF862 MMBTH10 (650 MHz) or BFR92 (5 GHz) MMBTH81L (600 MHz) or BFT92 (5 GHz)
Differential signal path to ADC
Existing & tested hybrid preamps Heko X Koeln PACAGA1A GANIL PA3.2X Milano All these prototypes are being tailored to AGATA and are under development
Existing & tested integrated preamps SFE16 (BiCMOS AMS 0.8 um) Saclay The chip alone shows very good resolution. New version is under development and will be tested with a segmented HPGe detector.
Conclusions Critical issues of AGATA preamplifiers Architecture of preamplifier Specifications Developments of hybrid/integrated integrated solutions New tests in near future