ECE 471/571 The CMOS Inverter Lecture-6 Gurjeet Singh
NMOS-to-PMOS ratio,pmos are made β times larger than NMOS
Sizing Inverters for Performance Conclusions: Intrinsic delay tp0 is independent of sizing of gate, and is determined by technology and inverter layout Making S infinitely large yields maximum obtainable performance gain, eliminating impact of any external load,and reducing delay to intrinsic one. Having S>> Cext/Cint works as good as infinite S
Propagation delay vs sizing factor
Sizing a Chain of Inverters ᵞ is proportionality factor. It is function of technology and is close to 1 for submicron processes f is effective fan out
Sizing of chain of inverters
Sizing of chain of inverters F is overall effective fan-out and strong function of number of inverters N
Choosing the Right Number of Stages in an Inverter Chain
The rise/fall time of the input signal is empirical contant, 0.25
Delay in presence of Interconnects Calculated using Elmore delay formula
Power, Energy, and Energy-Delay
Dynamic Dissipation due to Charging and Discharging Capacitances
Dynamic Power Each switching cycle takes fixed amount of energy f = maximum possible event rate of the inputs (most often its clock rate) P0->1= Probability of clock event results in 0 1 CEFF = Effective Capacitance(average capacitance switched every clock cycle)
Example 0.25um CMOS Process Clock Rate 400MHz Average load Capacitance 15fF/gate,assuming fanout of 4 At 2.5V per consumption per gate is 50uW For 1 million gates, consumption is 50 Watts!!!! All device not really switch
Dissipation Due to Direct-Path Currents
Dissipation Due to Direct-Path Current
Dissipation Due to Direct-Path Current
Energy-Delay Product
Static Consumption
Total Power Capacitive dissipation is dominant in this equation Keep direct path as small as possible by better design Leakage current is significant in latest technologies
The Power-Delay Product Average Energy Consumed per switching Event
Energy-Delay Product Take derivative wrt VDD and equate to 0, we get
Technology Scaling and its Impact on the Inverter Metrics
Wire Scaling
Summary Static CMOS combines NMOS and PMOS Almost Ideal VTC.Noise Margin approaches VDD/2 Propagation delay due to charging and discharging of Capacitor CL Power dissipation is dominated by dynamic power consumed by charging and discharging of capacitor. As transistor size reduces, interconnect components is taking larger share of propagation delay.
Combinational Logic Gates in CMOS
High-level Classification of Logic Circuits
Advantages of CMOS Low sensitivity to noise Good performance Low power consumption CMOS circuit styles falls in class of logic circuits called static circuits in which at every point in time each gate output is connected either to VDD or VSS
Complementary CMOS
Things to keep in mind while constructing PUN and PDN Think transistors as a switch controlled by gate signal Use NMOS devices for PDN and PMOS devices for PUN NMOS devices connected in series corresponds to AND function. While in parallel those corresponds to OR function
Things to keep in mind while constructing PUN and PDN Use De Morgan s theorem to create complementary dual networks Complementary gate is naturally inverting Number of transistors required to implement N-input logic gate is 2N
Two Input NAND Gate
VTC of NAND gate
Propagation Delay of CMOS Gates
Propagation delay of Four input NAND Gate
Disadvantages of Complementary CMOS Design Increase in complexity Larger implementation area Propagation delay deteriorates rapidly as a function of fan-in
Disadvantages of Complementary CMOS Design Large number of transistors increases overall capacitance of the gate Series connection causes slowdown
Design Techniques for Large Fan-in
Transistor Sizing Increase the size of transistor But increasing the transistor size also increases propagation delay
Progressive Transistor Sizing
Input Reordering
Logic Restructuring