March 6, 2006 Samsung K9HAG08U1M-PCB0 16 Gbit MLC NAND Flash Structural Analysis Report For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Technology Overview 1.5 Introduction 1.6 Device Summary 1.7 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Die Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Low-Voltage Transistors 3.7 Floating Gate Array Transistors 3.8 Peripheral High-Voltage Transistors 3.9 Isolation 3.10 Wells and Substrate 3.11 Redundancy Fuses 4 Memory Cell Analysis 4.1 Plan-View Analysis 4.2 Cross-Sectional Analysis Parallel to Bit Line 4.3 Cross-Sectional Analysis Parallel to Word Line
Structural Analysis 5 Materials Analysis 5.1 TEM-EDS of Dielectrics 5.2 TEM-EDS Analysis of Metals and Silicide 6 Critical Dimensions 6.1 Package and Die 6.2 Horizontal Dimensions 6.3 Vertical Dimensions 7 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Apple ipod nano (4 GB) Top 2.1.2 Apple ipod nano (4 GB) Bottom 2.1.3 Apple ipod nano (4 GB) During Teardown 2.1.4 Memory Module Top 2.1.5 Memory Module Bottom 2.1.6 Plan-View Package X-Ray 2.1.7 Side-View Package X-Ray 2.1.8 Die Photograph 2.1.9 Die Markings 2.1.10 Annotated Die Photograph Analysis Sites 2.2.1 Die Corner a 2.2.2 Die Corner b 2.2.3 Die Corner c 2.2.4 Die Corner d 2.2.5 Minimum Pitch Bond Pads 2.2.6 Bond Pad With ESD Protection 2.2.7 Fuse Array 2.2.8 Detail of Fuse Block 3 Process Analysis 3.1.1 General Die Structure 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad Edge 3.3.1 Passivation 3.3.2 IMD 2 3.3.3 IMD 1 3.3.4 PMD 3.4.1 Minimum Pitch Metal 3 3.4.2 Metal 3 Composition TEM 3.4.3 Minimum Pitch Metal 2 3.4.4 Metal 2 Composition TEM 3.4.5 Minimum Pitch Metal 1 3.4.6 Metal 1 Composition 3.5.1 Minimum Pitch Via 2s 3.5.2 Minimum Pitch Via 1s 3.5.3 Minimum Pitch Contacts to Poly 2 3.5.4 Metal 1 Strap 3.5.5 Minimum Pitch Tungsten Contacts 3.5.6 Metal 1 Contact to Source Line Contact 3.5.7 Minimum Width Poly 3 Contact 3.5.8 Poly 3 Bit Line Contact Top TEM
Overview 1-2 3.5.9 Poly 3 Bit Line Contact Bottom TEM 3.5.10 Minimum Pitch Poly 3 Contacts 3.5.11 Source Line Contact TEM 3.5.12 Minimum Width Interpoly Via TEM 3.5.13 Interpoly Via Si Etch 3.6.1 Peripheral MOS Transistors 3.6.2 Minimum Gate Length Peripheral LVNMOS Transistors 3.6.3 Minimum Gate Length Peripheral LVPMOS Transistors 3.7.1 Floating Gate Array Transistors Minimum Pitch Poly 3.7.2 Floating Gate Transistors TEM 3.7.3 ONO Interpoly Dielectric TEM 3.7.4 Tunnel Oxide Thickness TEM 3.8.1 HVMOS Write Driver Transistor 3.8.2 SCM of HVNMOS Write Driver Transistor 3.8.3 Tungsten S/D Contact (Left Side) TEM 3.8.4 Tungsten Contact (Right Side) TEM 3.8.5 HVMOS Gate Edge TEM 3.8.6 HVMOS Gate Oxide TEM 3.9.1 Minimum Width STI 3.9.2 Poly Over STI 3.10.1 Array Well Structure 3.10.2 SCM of Array Well Structure 3.10.3 SRP Profile of Array Well Structure 3.10.4 SRP Profile of Periphery P-Well 3.11.1 Fuse Window Intact Fuse Link 3.11.2 Detail of Fuse Link 4 Memory Cell Analysis 4.1.1 Die Photograph Die Deprocessed to Poly 2 Level 4.1.2 Write Drivers 4.1.3 Write Drivers (Area A) 4.1.4 Write Drivers (Area B) 4.1.5 Word Line Drivers 4.1.6 End of Word Lines and Word Line Drivers 4.1.7 Flash Array Deprocessed to Poly 2 (PMD 1 Intact) 4.1.8 Metal 1 Bit Lines 4.1.9 Poly 2 Word Lines and Bit Line Contacts (PMD 1 Intact) 4.1.10 Poly 1 Floating Gates 4.1.11 N + Diffusions and Source Line Contact 4.2.1 NAND Cell String 4.2.2 Floating Gate Cells
Overview 1-3 4.2.3 Bit Line Contact and Floating Gate Transistors Si Etch 4.2.4 Bit Line Select Transistor and Bit Line Contact TEM 4.2.5 Source Line Contact and Floating Gate Transistors Si Etch 4.2.6 Source Line Contact and Source Line Select Transistor TEM 4.3.1 Floating Gates (Parallel to Word Line) TEM 4.3.2 Detail of Floating Gate (Parallel to Word Line) TEM 4.3.3 Access Gate TEM 4.3.4 Bit Line Contacts 4.3.5 Source Line Contact 5 Materials Analysis 5.1.1 TEM-EDS Spectrum of Passivation 2 5.1.2 TEM-EDS Spectrum of Passivation 1 5.1.3 TEM-EDS Spectrum of IMD 2-2 5.1.4 TEM-EDS Spectrum of IMD 1-3 5.1.5 Metal 1 Sealant 5.1.6 TEM-EDS Spectrum of PMD 4 5.1.7 TEM-EDS Spectrum of PMD 1 5.1.8 Gate ARC 5.1.9 TEM-EDS Spectrum of Oxide Sidewall Spacer 5.2.1 TEM-EDS Spectrum of Metal 2 Cap 5.2.2 Metal 2 Barrier 5.2.3 TEM-EDS Spectra Comparing Gate Silicide to Tungsten and Silicon
Overview 1-4 1.2 List of Tables 1 Overview 1.6.1 Device Summary 1.7.1 Process Summary 3 Process Analysis 3.3.1 Dielectric Film Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Minimum Pitch Metals 3.5.1 Minimum Pitch Vias and Contacts 3.6.1 Peripheral Low Voltage Transistor Critical Dimensions 3.7.1 Floating Gate Storage Cell Transistor Critical Dimensions 3.8.1 Peripheral High-Voltage Transistor Critical Dimensions 3.10.1 Measured Well Depths 6 Critical Dimensions 6.1.1 Package and Die 6.2.1 Minimum Pitch Metals 6.2.2 Minimum Pitch Vias and Contacts 6.2.3 Peripheral Low-Voltage Transistor Critical Dimensions 6.2.4 Floating Gate Storage Cell Transistor Critical Dimensions 6.2.5 Peripheral High-Voltage Transistor Critical Dimensions 6.3.1 Vertical Dimensions
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