April 4, 2006 Samsung K9F2G08U0M-YCB0 2Gbit NAND Flash Device Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 Bond Pads 3.2 Passivation and Dielectrics 3.3 Pre-Metal Dielectric (PMD) 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Polysilicon 3.7 Isolation 3.8 Wells 4 Materials Analysis 4.1 EDS Analysis 4.2 SRP Analysis 5 Memory Cell Analysis 5.1 Plan View Analysis 5.2 Cross-Section Analysis Parallel to Bitline 5.3 Cross-Section Analysis Parallel to Wordline 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package Photograph 2.1.2 Bottom Package Photograph 2.1.3 Package X-Ray Plan-View 2.1.4 Package X-Ray Side-View 2.1.5 Die Photograph 2.1.6 Die Marking 2.1.7 Die Marking 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Typical Bond Pads 2.2.6 Detail of a Typical Bond Pad 2.2.7 Fuses 3 Process Analysis 3.0.1 General Device Structure 3.0.2 Die Edge 3.0.3 Die Seal 3.1.1 Typical Bond Pad 3.1.2 Detail of Bond Pad Structure 3.2.1 Device Passivation 3.2.2 Intermetal Dielectric (IMD) 3.3.1 Pre-Metal Dielectric 3.4.1 Minimum Pitch Metal 2 Lines 3.4.2 Metal 2 Cap 3.4.3 Metal 2 Barrier 3.4.4 Minimum Pitch Metal 1 Lines 3.4.5 TEM Image of Metal 1 Line 3.5.1 Vias and Contacts 3.5.2 Minimum Pitch Vias 3.5.3 Contacts to Poly and Diffusion 3.5.4 Tungsten Contacts to Poly Stack
Overview 1-2 3.5.5 W Contacts to N + Diffusion 3.5.6 Poly 4 Bitline Contacts Perpendicular to Bitline 3.5.7 TEM Image of Poly 4 Bitline Contact Parallel to Bitline 3.5.8 Top of Bitline Contact 3.5.9 Bottom of Bitline Contact 3.5.10 Source Line 3.6.1 Low-Voltage NMOS Periphery Transistors 3.6.2 Low-Voltage PMOS Periphery Transistor 3.6.3 High-Voltage PMOS Periphery Transistor 3.6.4 Stacked Gate Flash Cells 3.6.5 ONO Interpoly Dielectric 3.6.6 Gate Oxide 3.7.1 Minimum Width STI (Glass Etch Only) 3.8.1 Well Structure at End of Flash Array 4 Materials Anlaysis 4.1.1 EDS Analysis Reference 4.1.2 EDS Spectrum of Metal 2 Cap 4.1.3 EDS Spectrum of Metal 2 Barrier 4.1.4 EDS Spectrum of Metal 2 Adhesion Layer 4.1.5 EDS Spectrum of Silicide of Top of Bitline Poly Contact 4.1.6 EDS Spectrum of Passivation 2 4.1.7 EDS Spectrum of Passivation 1 4.1.8 EDS Spectrum of IMD 1-2 4.1.9 EDS Spectrum of PMD 4 4.1.10 EDS Spectrum of Sidewall Spacer 4.1.11 EDS Spectrum of Poly 2 Gate Silicide 4.2.1 SRP Analysis Reference 4.2.2 Spreading Resistance Profile through N-Well 4.2.3 Spreading Resistance Profile through P-Well Periphery 4.2.4 Spreading Resistance Profile through Embedded P-Well Flash Array
Overview 1-3 5 Memory Cell Analysis 5.1.1 Flash Array Metal 1 5.1.2 Metal 1 Image with Cross-Section Reference 5.1.3 Flash Array Poly Control Lines 5.1.4 Flash Array Floating Gates 5.1.5 Detail of Floating Gates 5.2.1 Flash Array Parallel to Bitline 5.2.2 Bitline Contact 5.2.3 Source Line 5.2.4 Floating Gate Cells 5.3.1 Flash Array Source Line 5.3.2 Flash Array Wordline 5.3.3 Flash Array Detail of Wordline 5.3.4 Bitline Select Transistor Contact and Bitline Contacts 6 Critical Dimensions Report Evaluation 1.2 List of Tables 3.2.1 Passivation and IMD Vertical Dimensions 3.3.1 Premetal Dielectric Vertical Dimensions 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions
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