N-channel 600 V, 0.115 Ω typ., 22 A MDmesh M2 Power MOSFET in a PowerFLAT 8x8 HV package Datasheet - production data Features Order code V DS @ T Jmax R DS(on)max I D 5 STL33N60M2 650 V 0.135 Ω 22 A 4 3 2 1 PowerFLAT 8x8 HV Features Extremely low gate charge Excellent output capacitance (C OSS ) profile 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packaging STL33N60M2 33N60M2 PowerFLAT 8x8 HV Tape and reel November 2015 DocID024325 Rev 3 1/15 This is information on a product in full production. www.st.com
Contents STL33N60M2 Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.1 Electrical characteristics (curves)... 6 3 Test circuits... 8 4 Package mechanical data... 9 4.1 PowerFLAT 8x8 HV package mechanical data... 10 5 Packaging mechanical data... 12 5.1 PowerFLAT 8x8 HV packaging mechanical data... 12 6 Revision history... 14 2/15 DocID024325 Rev 3
Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 25 V I D (1) I D (1) I DM (2) Drain current (continuous) at T C = 25 C 22 A Drain current (continuous) at T C = 100 C 13.8 A Drain current (pulsed) 88 A P TOT Total dissipation at T C = 25 C 150 W I AR E AS Avalanche current, repetitive or not-repetitive (pulse width limited by T j max) Single pulse avalanche energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 4 A 1100 mj dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns T stg Storage temperature - 55 to 150 C T j Operating junction temperature 150 C Notes: (1) The value is limited by package. (2) Pulse width limited by safe operating area. (3) ISD 22 A, di/dt 400 A/µs, V DS(peak) < V (BR)DSS, V DD = 400 V. (4) VDS 480 V. Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 0.83 C/W R thj-amb (1) Thermal resistance junction-ambient max 45 C/W Notes: (1) When mounted on FR-4 board of inch², 2oz Cu. DocID024325 Rev 3 3/15
Electrical characteristics STL33N60M2 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS V GS(th) R DS(on) Drain-source breakdown voltage Zero gate voltage drain current Gate-body leakage current Gate threshold voltage Static drain-source on- resistance V GS = 0, I D = 1 ma 600 V V GS = 0, V DS = 600 V 1 µa V GS = 0, V DS = 600 V, T C=125 C 100 µa V DS = 0, V GS = ± 25 V ±10 µa V DS = V GS, I D = 250 µa 2 3 4 V V GS = 10 V, I D = 11 A 0.115 0.135 Ω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance - 1781 - pf C oss Output capacitance V DS = 100 V, f = 1 MHz, - 85 - pf Reverse transfer V GS = 0 C rss - 2.5 - pf capacitance C oss eq. (1) R G Equivalent output capacitance Intrinsic gate resistance V DS = 0 to 480 V, V GS = 0-135 - pf f = 1 MHz open drain - 5.2 - Ω Q g Total gate charge V DD = 480 V, I D = 26 A - 45.5 - nc Q gs Gate-source charge V GS = 10 V - 9.9 - nc Q gd Gate-drain charge (see Figure 15: "Gate charge test circuit") - 18.5 - nc Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% V DSS. Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 300 V, I D = 13 A - 16 - ns t r Rise time R G = 4.7 Ω, V GS = 10 V - 9.6 - ns t d(off) Turn-off delay time (see Figure 14: "Switching times test circuit for resistive - 109 - ns t f Fall time load") - 9 - ns 4/15 DocID024325 Rev 3
Table 7: Source drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 22 A I SDM (1) V SD (2) Source-drain current (pulsed) - 88 A Forward on voltage I SD = 26 A, V GS = 0-1.6 V t rr Reverse recovery time I SD = 26 A, di/dt = 100 A/µs - 375 ns Q rr Reverse recovery charge V DD = 60 V (see Figure 17: " Unclamped inductive load - 5.6 µc I RRM Reverse recovery current test circuit") - 30 A t rr Reverse recovery time I SD = 26 A, di/dt = 100 A/µs - 478 ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C - 7.7 µc I RRM Reverse recovery current (see Figure 17: " Unclamped inductive load test circuit") - 32.5 A Notes: (1) Pulse width limited by safe operating area. (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID024325 Rev 3 5/15
Electrical characteristics 2.2 Electrical characteristics (curves) Figure 2: Safe operating area STL33N60M2 Figure 3: Thermal impedance K δ=0.5 0.2 0.1 10-1 0.05 0.02 Single pulse 0.01 Z th = K*R thj-c δ= t p /Ƭ 10-2 t p Ƭ 10-5 10-4 10-3 10-2 tp(s) Figure 4: Output characteristics GIPG080720141147MT ID(A) VGS=7, 8, 9, 10V 60 6V Figure 5: Transfer characteristics GIPG080720141423MT ID (A) 60 50 50 VDS=17V 40 30 20 5V 40 30 20 10 4V 10 0 0 5 10 15 20 VDS(V) 0 0 2 4 6 8 10 VGS(V) Figure 6: Gate charge vs gate-source voltage GIPG230420141134MT Figure 7: Static drain-source on-resistance GIPG090720140852MT RDS(on) (Ω) VGS=10V 0.122 0.120 0.118 0.116 0.114 0.112 0.110 0 5 10 15 20 ID(A) 6/15 DocID024325 Rev 3
Figure 8: Capacitance variations GIPG230420141135MT Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature GIPG230420141136MT Figure 10: Normalized on-resistance vs temperature RDS(on) GIPG090720140955MT (norm) VGS=10V 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5-50 -25 0 25 50 75 100 TJ( C) Figure 11: Normalized V (BR)DSS vs temperature V(BR)DSS (norm) 1.11 1.09 1.07 1.05 1.03 1.01 0.99 0.97 0.95 ID=1m A GIPG090720141001MT 0.93 0.91-50 -25 0 25 50 75 100 TJ( C) Figure 12: Source-drain diode forward characteristics GIPG090720141014MT VSD(V) Figure 13: Output capacitance stored energy GIPG230420141137MT 1.4 1.2 TJ=-50 C 1 0.8 0.6 0.4 0.2 TJ=150 C TJ=25 C 0 0 2 4 6 8 10 12 14 16 18 20 ISD(A) DocID024325 Rev 3 7/15
Test circuits STL33N60M2 3 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VGS VD RG RL + D.U.T. 2200 µf 3.3 µf VDD PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit 25Ω G A D D.U.T. S B A FAST DIODE B A B L=100µH D 3.3 1000 µf + µf VDD VD L + 2200 µf 3.3 µf VDD G ID RG S D.U.T. Vi D.U.T. GND1 GND2 Pw GND1 GND2 AM15858v1 Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/15 DocID024325 Rev 3
Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID024325 Rev 3 9/15
Package mechanical data 4.1 PowerFLAT 8x8 HV package mechanical data Figure 20: PowerFLAT 8x8 HV package outline STL33N60M2 8222871_Rev_3_ A 10/15 DocID024325 Rev 3
Dim. Package mechanical data Table 8: PowerFLAT 8x8 HV mechanical data mm Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 0.05 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e 2.00 L 0.40 0.50 0.60 Figure 21: PowerFLAT 8x8 HV footprint All dimensions are in millimeters. DocID024325 Rev 3 11/15
Packaging mechanical data STL33N60M2 5 Packaging mechanical data 5.1 PowerFLAT 8x8 HV packaging mechanical data Figure 22: PowerFLAT 8x8 HV tape Figure 23: PowerFLAT 8x8 HV package orientation in carrier tape 12/15 DocID024325 Rev 3
Figure 24: PowerFLAT 8x8 HV reel Packaging mechanical data DocID024325 Rev 3 13/15
Revision history STL33N60M2 6 Revision history Table 9: Document revision history Date Revision Changes 26-Jun-2013 1 First release. 23-Jul-2014 2 20-Nov-2015 3 Updated the title, the features and the description in cover page. Document status promoted from preliminary data to production data. Updated Figure 1: "Internal schematic diagram", Section 1: "Electrical ratings", Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)" Updated Section 3: "Test circuits", Section 4.1: "PowerFLAT 8x8 HV package mechanical data".. Updated: cover image and Figure 1: "Internal schematic diagram" Table 2: "Absolute maximum ratings", Table 3: "Thermal data" and Table 6: "Switching times" Updated: Figure 3: "Thermal impedance" Updated: Section 5: "Test circuits" Updated: Section 6.1: "PowerFLAT 8x8 HV package mechanical data" Minor text changes 14/15 DocID024325 Rev 3
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