March 5, 2007 OmniVision OV2640 1/4-Inch 2 Megapixel CMOS Image Sensor (OV253AI Die Markings) TSMC 0.13 µm Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product Identification, Image Sensor Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Transistors and Poly 3.6 Isolation 3.7 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan View Analysis Active Pixels 4.3 Pixel Cross-Sectional Analysis Parallel to Transfer Lines 4.4 Pixel Cross-Sectional Analysis Parallel to Row Select 4.5 Microlens and Color Filter Analysis 5 Memory Cell Analysis 5.1 6T SRAM Overview and Schematic 5.2 6T SRAM Plan View Analysis 6 Critical Dimensions 6.1 Package, Die and Bond Pad Sizes 6.2 Dielectrics, Metals, Vias and Contacts 6.3 Transistors and Poly, Isolation and Wells 6.4 Pixel Dimensions
Imager Process Review 7 Statement of Measurement Uncertainty 8 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Sony Ericsson V630i Front 2.1.2 Sony Ericsson V630i Back 2.1.3 Sony Ericsson V630i Main Board Back 2.1.4 Image Sensor Assembly Top 2.1.5 Image Sensor Assembly Side 2.1.6 OV2640 Top Package View 2.1.7 OV2640 Bottom Package View 2.1.8 Plan View Package X-Ray 2.1.9 OV2640 Die 2.1.10 Die Markings 2.1.11 Analysis Sites 2.2.1 Package Cross Section 2.2.2 Die Corner A 2.2.3 Die Corner B 2.2.4 Die Corner C 2.2.5 Die Corner D 2.2.6 Die Feature A 2.2.7 Die Feature B 2.2.8 Die Feature C 3 Process Analysis 3.1.1 General View of OV2640 3.1.2 Pad Extension Layer and Bond Pad 3.2.1 Passivation 3.2.2 IMD 2 3.2.3 IMD 1 3.2.4 PMD 3.3.1 Minimum Pitch Metal 3 3.3.2 Minimum Pitch Metal 2 3.3.3 Minimum Pitch Metal 1 Logic 3.3.4 Minimum Pitch Metal 1 Pixel Array 3.4.1 Minimum Pitch Via 2s 3.4.2 Minimum Pitch Via 1s 3.4.3 Minimum Pitch Contacts to Poly 2 3.4.4 Minimum Pitch Contacts to Diffusion 3.5.1 MOS Transistor Oxide Etch 3.5.2 Minimum Gate Length NMOS Logic Transistors 3.5.3 Minimum Gate Length PMOS Logic Transistors 3.6.1 Poly over STI 3.6.2 Minimum Width STI 3.7.1 SCM of Peripheral Wells 3.7.2 SRP Analysis Sites
Overview 1-2 3.7.3 SRP of Peripheral N-Well (Location 1) 3.7.4 SRP of Peripheral P-well (Location 2) 3.7.5 SRP of Array Well Structure 4 Pixel Analysis 4.1.1 4-Shared Pixel Schematic (2T equivalent) 4.2.1 Pixel Array RBG Bayer Patterned Color Filters 4.2.2 Pixel at Metal 3 4.2.3 Aperture Shift Top Left Corner of Array 4.2.4 Aperture Shift Top Right Corner of Array 4.2.5 Pixel at Metal 2 4.2.6 Pixel at Metal 1 4.2.7 Pixel at Poly 4.2.8 Pixel at Diffusion 4.2.9 Bevel SCM of Pixel 4.3.1 Pixel at Poly Planes of Cross-Sectioning (Parallel to Transfer Lines) 4.3.2 Pixel Overview 4.3.3 Reset Gate Oxide Etch 4.3.4 Detail of Reset Gate Oxide Etch 4.3.5 Transfer Gate Oxide Etch 4.3.6 Detail of Transfer Gate Si Etch 4.3.7 SCM of Photocathode 4.3.8 V SS or V REF Contacts 4.3.9 Pixel Aperture Left 4.3.10 Pixel Aperture Shift 4.3.11 Edge of Array Microlens Shift 4.4.1 Pixel at Poly Planes of Cross-Sectioning (Parallel to Row Select) 4.4.2 Reset or Source Follower Gate 4.4.3 Detail of Reset or Source Follower Gate 4.4.4 Pixel Overview TEM 4.4.5 Transfer Gates TEM 4.4.6 Gate Wrap TEM 4.4.7 Transfer Gate Oxide TEM 4.4.8 Contact Etch Stop/AR Layer 4.5.1 Microlens Radius of Curvature 4.5.2 Pixel Field of View 4.5.3 Red-Green Pixel Pairs 4.5.4 Blue-Green Pixel Pairs 5 Memory Cell Analysis 5.1.1 6T SRAM Schematic 5.2.1 6T SRAM at Metal 2 5.2.2 6T SRAM at Metal 1 5.2.3 6T SRAM at Poly 5.2.4 6T SRAM at Diffusion
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die and Bond Pad Sizes 3 Process Analysis 3.2.1 Dielectric Thicknesses 3.3.1 Metallization Vertical Dimensions 3.3.2 Metallization Observed Minimum Horizontal Dimensions 3.4.1 Via and Contact Dimensions 3.5.1 Peripheral Transistor and Poly Dimensions 3.6.1 STI Critical Dimensions 3.7.1 Die Thickness and Well Depths 4 Pixel Analysis 4.5.1 Pixel Horizontal Dimensions 4.5.2 Pixel Transistor Dimensions 4.5.3 Pixel Vertical Dimensions 6 Critical Dimensions 6.2.1 Dielectric Thicknesses 6.2.2 Metallization Vertical Dimensions 6.2.3 Metallization Observed Minimum Horizontal Dimensions 6.2.4 Via and Contact Dimensions 6.3.1 Peripheral Transistor and Poly Dimensions 6.3.2 STI Critical Dimensions 6.3.3 Die Thickness and Well Depths 6.4.1 Pixel Horizontal Dimensions 6.4.2 Pixel Transistor Dimensions 6.4.3 Pixel Vertical Dimensions
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