A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.6, DECEMBER, 2018 ISSN(Prin) 1598-1657 hps://doi.org/10.5573/jsts.2018.18.6.685 ISSN(Online) 2233-4866 A Sereo Audio Dela-Sigma DAC wih 40-kHz Bandwidh and 103-dB SNR Han Yang, Jun Soo Cho, Yujin Park, Hyunjong Kim, and Suhwan Kim Absrac A wide-band and low-noise sereo delasigma (ΔΣ) digial-o-analog converer (DAC) for audio applicaions is proposed. A muli-bi quanizer wih daa-weighed averaging is used o reduce quanizaion noise and a half-band finie impulse response filer is designed o increase he speed of he ΔΣ modulaor. A direc-charge-ransfer swichedcapacior DAC and a rack-and-hold circui wih a deglich iming are used o improve he operaing speed and he lineariy of he audio DAC. The chip is fabricaed wih a 0.13-μm CMOS process, which uses he supply volages of 1.2 V for he digial domain and 3.3 V for he analog domain. The experimenal resuls show ha our audio DAC achieves 40-kHz bandwidh, 103-dB A-weighed signal-o-noise raio, and - 85-dB oal harmonic disorion and noise. Index Terms Digial-o-analog converer, low-noise, wide-band, dela-sigma modulaor, swichedcapacior circuis I. INTRODUCTION Recenly, as he marke for arificial inelligen speakers has expanded and become popular, high-qualiy audio coder-decoder (CODEC) is required. The delasigma (ΔΣ) digial-o-analog converer (DAC), one of he key componens of he CODEC, is essenial for generaing high-performance audio signals wih a signalo-noise raio (SNR) over 100 db [1-3]. An ani-aliasing Manuscrip received Mar. 20, 2018; acceped Nov. 5, 2018 Elecrical Engineering, Seoul Naional Univ., Seoul, Korea E-mail : suhwan@snu.ac.kr filer (AAF) is needed o reduce ou-of-band noise (OBN). A low-sampling rae requires a high-order seep filer. However, making he roll-off very seep can cause phase shif or resonan peaks. Sampling a higher frequencies allows he AAF o be implemened above he audible frequency range, hus alleviaing filer design condiions. In oher words, 96 khz or 192 khz sampling frequency is used for beer sound qualiy [4, 5]. An audio ΔΣ DAC is composed of a digial fron-end (DFE) and an analog oupu sage. The DFE consiss of a frequency inerpolaion filer and a ΔΣ modulaor. The digial inpu signal is up-sampled wih an oversampling raio (OSR) in he inerpolaion filer. And he ΔΣ modulaor suppresses he quanizaion noise by noiseshaping. Muli-level modulaion reduces he quanizaion noise more han 1-bi modulaion [3, 6]. Bu i requires a dynamic elemen maching (DEM) such as daa-weighed averaging (DWA) o suppress he nonlineariies caused by he mismach among elemens [7, 8]. Increasing he OSR also helps o achieve high SNR by spreading he quanizaion noise over a wider frequency band. However, his requires faser, more power-inensive digial processing which is cosly. The analog oupu sage consiss of an inernal DAC and a reconsrucion low-pass filer (LPF). I produces an analog audible signal and filers OBN. There are wo ways o implemen: a curren-seering [2, 3] and a swiched-capacior (SC) [9, 10]. The curren-seering ype has he advanages of low-power consumpion and small area, bu i is very sensiive o clock jier. To achieve low-power consumpion as well as he clock jier insensiiviy, a direc-charge-ransfer SC DAC (DCT-SC DAC) [11, 12] is presened. However, if he oupu of he SC DAC is in non-reurn-o-zero (NRZ)

686 HAN YANG e al : A STEREO AUDIO DELTA-SIGMA DAC WITH 40-kHz BANDWIDTH AND 103-dB SNR Righ-Channel Lef-Channel Sereo Digial Inpu fs 20 Digial Fron-End Inerpolaion Filer 64fs 20 ΔΣ Modulaor 64fs 5 Thermomeer Decoder & DWA 64fs 30 Analog Oupu Sage Inernal DAC Track-and- Hold Reconsrucion Filer Sereo Analog Oupu Fig. 1. Block diagram of he proposed sereo audio dela-sigma DAC. forma, whose oupu is no rese periodically, inersymbol inerference (ISI) issues can occur. The ISI is caused by dynamic error sources such as incomplee oupu seling and remained charge a parasiic capaciances [6]. The inernal DAC of reurn-o-zero (RZ) formaed oupu is less sensiive o he ISI, bu here is anoher problem of reduced signal power and increased harmonic disorion when he oupu is applied direcly o he LPF. In his paper, we propose a 40-kHz bandwidh and 103-dB SNR audio DAC fabricaed in he 0.13-μm CMOS process. To achieve hese performances, a 64 inerpolaion filer and a 5 h -order ΔΣ modulaor wih a 5- bi quanizer using a digial half-band finie impulse response (FIR) filer is designed in he DFE. The DCT- SC DAC wih he opimal bias curren analysis of he opamp enhances he operaing speed. Also, he inernal DAC wih RZ-formaed oupu reduces he ISI. A rackand-hold (T/H) circui wih deglich iming [13] also improves he signal power and he lineariy. The res of his paper is organized as follows: Secion II shows he archiecure of our audio ΔΣ DAC sysem. In secion III, proposed circui and analysis are described. Secion IV and V show he experimenal resuls and conclusion. II. ARCHITECTURE Fig. 1 shows he block diagram of he proposed audio ΔΣ DAC which consiss of he DFE and he analog oupu sage. In he DFE, he frequency of he 20-bi inpu signal is increased by he inerpolaion filer as insering zero samples beween he inpu daa [16]. Then he digial FIR filer removes he aliases and smoohens he zero-padded daa. The sampled inpu signal a 96 khz is up-sampled by a facor of OSR which is 64 wih 2 sages of cascaded FIR filers and a sample-and-hold regiser. V V Digial Inpu NRZ Analog Oupu Digial Inpu RZ Analog Oupu (a) (b) ISI Errors No ISI Error Fig. 2. Oupu waveform and ISI errors of (a) NRZ ype DAC, (b) RZ ype DAC. The in-band noise is suppressed by he oversampling and noise-shaping principle of he digial ΔΣ modulaor. To expand he inpu signal bandwidh up o he 40 khz, he sampling rae of he ΔΣ modulaor f s is se o 96 khz. The operaing clock of he ΔΣ modulaor f clk is 6.144 MHz wih he OSR of 64. A 5-bi quanizer is used in our ΔΣ modulaor o reduce he quanizaion noise, suppress he idle ones, and improve he sabiliy of he ΔΣ modulaion loop. The mismach among he quanizers is averaged by DWA echnique [7, 8], which scrambles he 30-bi oupu codes of he hermomeer decoder. The inernal DAC convers he decoded and shuffled 30-bi digial hermomeer codes ino a coninuousampliude signal. The DCT-SC DAC has advanages such as less sensiiviy o clock jier noise and elemen mismaches compared o he curren-seering DAC [11, 12]. The oupu of he inernal DAC is RZ forma ha is robus o he ISI [6]. As shown in Fig. 2(a), he NRZ forma oupu can cause differen oupus wih he same

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.6, DECEMBER, 2018 687 20-b D in f s =96 khz f s Zero Inserion 2f s Half-Band FIR Filer 2f s Zero Inserion 4f s Half-Band FIR Filer 4f s 16X Sample-and-Hold 64f s D ou (a) x[n] f(0) f(1) f(2) f(l-2) f(l-1) y[n] Fig. 3. (a) Signal flow diagram of he inerpolaion filer, (b) block diagram of he half-band FIR filer. (b) inpus due o he incomplee seling or memory effecs. However, he RZ forma oupu guaranees he same oupus for he same inpus by placing rese inervals on each inpu samples as shown in Fig. 2(b). I only causes a gain error, which can be easily correced laer. The oupu of he inernal DAC is sampled and applied o he reconsrucion filer. The reconsrucion filer is ypically implemened as LPF. This can be implemened as off-chip [12, 13] or on-chip [10, 14]. If he coninuous-ime LPF is followed by he discree-ime SC inernal DAC, he signal power is reduced by he periodic oupu rese of he inernal DAC. This problem does no occur when he inernal DAC is implemened by a coninuous-ime curren-adjusmen inernal DAC. To overcome his problem wihou losing he SC circui advanages such as good ISI and device maching characerisics, we added a T/H circui wih deglich iming beween he inernal DAC and he reconsrucion LPF [15]. A Sallen-Key ype filer realizes a 2 nd -order LPF o suppress OBN over 40 khz. The reduced quanizaion noise of he 5-bi quanizer and 64 OSR relaxes he LPF specificaions. Two idenical singleended 2 nd -order Sallen-Key filers are designed in each channel ha can drive a 20-k Ω and 5-pF off-chip load. III. CIRCUIT IMPLEMENTATION 1. Digial Fron-end Fig. 3(a) shows he frequency inerpolaion process of he 20-bi digial inpu signal which is sampled a f s of Table 1. Specificaions of 1 s /2 nd half-band filers Parameer Value Order 144 Oversampling raio 2 Passband ripple 4 10-5 db Sopband Sopband aenuaion 0.546 f s -110 db 96 khz. The inerpolaion filer consiss of 2 sages of cascaded half-band FIR filers [17] and a sample-andhold regiser. Firs, zeros are insered beween adjacen digial daa of he inpu signal o generae a wice sampling frequency signal. As shown in Fig. 3(b), he generaed signal is smoohened by he half-band FIR filer ha removes imaginary componens. Table 1 shows he specificaions of he 1 s and 2 nd half-band FIR filers ha are idenical. The order of he half-band FIR filer is 144, bu he calculaion is performed 72 imes using 36 coefficiens. The quadruple sampling frequency signal afer wo sages of cascaded half-band FIR filers is applied o he sample-and-hold regiser a a 16 imes upsampling rae. The final oversampled oupu daa is hen generaed a a frequency of 64f s, which is 6.144 MHz. Fig. 4 shows he archiecure of he 5 h -order digial ΔΣ modulaor. The signal and noise ransfer funcions of he ΔΣ modulaor pass he audio-band signal up o 40 khz and move he quanizaion noise o he ou-of-band. The coefficiens, a 1 o a 5, and b 1 are implemened by mulipliers and he delay unis in he inegraors are realized by regisers. The up-sampled signals are runcaed by he 5-bi quanizers. To alleviae he

688 HAN YANG e al : A STEREO AUDIO DELTA-SIGMA DAC WITH 40-kHz BANDWIDTH AND 103-dB SNR 30-bi Thermomeer Decoder D IN b 1 1 z 1 z 1 DWA D OUT 5-bi Quanizer a1 a2 a3 a4 a5 Fig. 4. The archiecure of he 5 h -order digial ΔΣ modulaor. D IN 30 V REFP V REFN V REFP V REFN V REFP V REFN sum din[29:0] din[29:0] ou 30 elemens cap array sum sum 30 elemens cap array ou Φ2 din[29]*φ1d din[29]*φ1d Φ2 din[28]*φ1d din[28]*φ1d din[0]*φ1d din[0]*φ1d disorion problems caused by elemen mismaches in he inernal DAC, he 31-level hermomeer code convered from 5-bi daa is shuffled by he DWA. I selecs he elemens sequenially according o he inpu, which resuls in averaging he mismach among elemens of he inernal DAC. 2. Analog Oupu Sage C s[29] C s[28] C s[0] Fig. 5. 31-level DCT-SC DAC. Φ2 Fig. 5 shows he fully-differenial 31-level DCT-SC DAC design. The uni capaciors C s [29:0] sampled a V REFP or V REFN depending on he digial inpus a Φ 1, and are fed back a Φ 2 o produce an analog oupu Φ 1 Φ1 ou Φ 2 Φ 2 Φ 1 Φ 1D Φ 2 Φ 1 C f C f Φ 1 Ou+ Ou- value. The oal feedback capaciance a Φ 2 is (C s +C f ) where he C f is a fixed feedback capacior. Due o he naure of he SC circui, he clock jier has negligible effecs on he inernal DAC performance unless he edges of he non-overlapping clocks, Φ 1 and Φ 2, are no swapped. In he capacior array, Φ 1D, whose falling edge is delayed from Φ 1, is used for he boom-plae sampling. Oherwise, any on-resisance mismach among swiches ha urn on a Φ 1D in he capacior array can cause signal-dependen disorions due o charge injecions or hermal noise unbalances. The hermomeerdecoded and shuffled digial inpus from he DFE reduce he mismach of C s [29:0] and improve he lineariy. By reusing he sampling capaciors as feedback capaciors, he power consumpion o charge or discharge he feedback capaciors is decreased. The auo-zeroing swich beween he opamp inpu and he oupu removes he offse and low-frequency flicker noise even if hey vary wih emperaure change or aging. The size of capaciors is deermined by he kt/c noise conribuion. The analog oupu volage of he inernal DAC is as follows: 29 1 V = å D [ n] C ( V - V ) (1) C + C = OUT IN s REFP REFN s f n 0 In our design, he sampling rae of he DCT-SC DAC is 6.144 MHz, which is muliplied by he OSR of 64 a he Nyquis sampling frequency of 96 khz. The uni capaciance is 628 ff for boh C s and C f, so ha heir raio becomes consisen agains process variaions. The oal sampling capaciance is 18.8 pf provided by 30 uni capaciors, and he C f is 22.6 pf. V REFN is acually ground level and V REFP is 3.3 V ha is he same as he analog supply volage, and he differenial oupu swing is 3.0 V pp.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.6, DECEMBER, 2018 689 C2 ID VBP ID VBP IN+ Φ3 R1 R2 Ou+ Cs C1 VCP VCP VOUT- VOUT+ VIN+ VCN Cs C1 VIN- IN- Ou- Φ3 R1 R2 VCMFB VCMFB C2 (a) (a) V VOUT,DAC VOUT,T/H Φ1 VOUT,Filer w/o T/H Φ2 VOUT,Filer w/ T/H V OUT Φ3 Slew Linear Seling VOUT,T/H V arge V slew V dynamic_error (b) VOUT,DAC Glich when Φ3=Φ2 Fig. 7. (a) A block diagram, (b) oupu waveforms, (c) clock iming diagram of he T/H and he 2 nd -order Sallen-Key filer. (c) slew lin (b) Fig. 6. (a) Differenial folded-cascode OTA, (b) oupu seling behavior of he OTA. se I D = CL Rb ( - ) se -ln 2 slew -B ( ) (3) Fig. 6(a) depics he differenial folded-cascode operaional ransconducance amplifier (OTA) used in he inernal DAC. The bias curren I D of he OTA should be large enough o diminish he oal harmonic disorion (THD) bu should be small o minimize he overall chip power dissipaion. Alhough he DCT-SC DAC is a power-efficien srucure, we have furher opimized he curren consumpion of he OTA. Fig. 6(b) shows he oupu seling ime of he OTA ha consiss of slew region and linear seling region. The required bias curren for he slew region is deermined by load capaciance C L, slewing volage V slew, and slewing ime slew as follows: I C V L slew D = (2) slew The required bias curren for he linear seling region is deermined by load capaciance C L, reurn facor b, arge effecive resoluion B, oal seling ime se, and g m /I D raio R as follows: From (3) and (4) slew is calculaed as follows: slew Vslew Rb se = (4) - ln 2 + V Rb -B ( ) slew The opimal bias curren I D of he OTA is hen compued by subsiuing slew ino eiher (2) or (3). The image componens produced by he inernal DAC are removed, and he audio oupu signal is generaed by he 2 nd -order Sallen-Key filer as shown in Fig. 7(a). The sampling capacior C s is 6 pf o suppress he kt/c noise and he 3-dB bandwidh is 400 khz o pass he inpu signal frequency up o 40 khz. The filer is designed wih a drivabiliy of 20-k Ω and 5-pF load and a differenial oupu swing of 3.0 V pp. The qualiy facor is designed o be 0.5 considering lile signal droop. Since he inernal DAC is an RZ ype whose oupu is rese a Φ 1, applying he oupu of he inernal DAC direcly o he LPF diminishes he signal power by 6 db since i averages boh he meaningful inpu signal and rese values. To overcome his problem, he T/H circui is

690 HAN YANG e al : A STEREO AUDIO DELTA-SIGMA DAC WITH 40-kHz BANDWIDTH AND 103-dB SNR Tes Board 2230 μm Inernal DAC (L-ch) 1600 μm Inerpolaion Filer and ΔΣ Modulaor (L/R-ch) T/H and LPF (L-ch) Inernal DAC (R-ch) T/H and LPF (R-ch) Inerpolaor + ΔΣ Modulaor Sereo Audio DAC Chip Sereo Balanced Connecors Righ-channel (R-ch) OUT+ Lef-channel (R-ch) OUT- Inernal DAC (L-ch) OUT+ (L-ch) OUT- I2S Conrol Audio Analyzer Daa Fig. 8. Die micrograph. Fig. 10. Measuremen seup. Fig. 9. PCB board. Fig. 11. Measuremen environmen. insered beween he inernal DAC and he LPF. As shown in Fig. 7(b), he oupu signal is improved by 6 db when he T/H circui is used compared o he case when he T/H circui is no used. There is anoher facor ha degrades he lineariy performance of he audio DAC. If Φ 2 is used for he T/H sampling swich, oupu gliches occur because he reconsrucion filer racks he incompleely seled inpu signal as shown in Fig. 7(c). To solve his issue, deglich iming clock Φ3 is used for he T/H circui operaion. The rising edge of Φ3 is laer han Φ 2 o wai unil he oupu of he inernal DAC is seled sufficienly. To ensure seling of more han 99 % of he inernal DAC oupu, Φ3 goes high afer Φ 2 goes high wih a delay ime ( slew + 5 ), where slew and are he slew ime and he ime consan of he inernal DAC, respecively. The falling edge of Φ3 is slighly faser han ha of Φ 2 o ensure ha he oupu of he inernal DAC is no rese. The T/H circui is designed o be eiher acivaed or bypassed o verify he validiy of he circui and he deglich iming. IV. EXPERIMENTAL RESULTS Fig. 8 is a die micrograph fabricaed in 0.13-μm CMOS process, and he chip has wo idenical channels for sereo audio signal processing wih he acive area of 2,230 μm 1,600 μm. The DFE is synhesized ino a single block for wo channels. Fig. 9 is a es PCB board wih he fabricaed chip in he cener. Fig. 10 and 11 shows he measuremen seup. Digial inpu signals are applied o our audio DAC chip wih he iner-ic sound (I2S) forma. The analog oupu signals are conneced o he audio analyzer hrough sereo balanced connecors. The measured in-band specrum wih - 12-dBFS inpu signal is shown in Fig. 12. The fas Fourier ransform (FFT) is performed wih 16,384 poins. The black-colored graph indicaes he FFT specrum of he proposed audio DAC using T/H circui and deglich iming. The gray-colored graph is he FFT specrum when he oupu signal of he inernal DAC is direcly conneced o he LPF bypassing he T/H circui. Thanks o he T/H circui and he deglich iming, he signal

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.6, DECEMBER, 2018 691 Table 2. Performance summary and comparison No using T/H nor deglich iming clock Using T/H and deglich iming clock Fig. 12. Measured in-band specrum wih a - 12 dbfs inpu signal. Process [10] [14] This work 0.13 μm CMOS 0.13 μm CMOS 0.13 μm CMOS Supply Volage (V) 1.2/3.3 1.2/2.7 1.2/3.3 Bandwidh (Hz) 20 20k 20 20k 20-40k Sampling Frequency (khz) Operaing Clock Frequency (MHz) 44.1 48 96 5.64 1.54 6.14 Oupu Swing (V pp,diff) 2.5 2.3 3.0 SNR (db(a)) 97 102 103 THD+N (db) -85-85 -85 Power Consumpion (mw) 14.5 8 41.4 FOM SNR 9.76E+10 3.15E+11 1.36E+11 Fig. 13. Measured THD+N according o he inpu signal power. ±0.6 db ± 0.6 db as he inpu frequency changes from 20 o 45 khz a he 96-kHz sampling rae. The proposed audio DAC achieves 103-dB A-weighed SNR a a 1-kHz inpu and consumes 41.4 mw per channel. Table 2 summarizes he performance and compares wih oher sereo audio DACs ha are fabricaed in 0.13- μm CMOS process. The figure of meri (FOM) of he audio DAC is defined as FOM SNR =SNR BW/Power [18]. The oal power consumpion of our chip is larger han oher sudies in Table 2, bu i is caused by he 2x higher bandwidh as you can see he FOM SNR is beer han [10]. The higher FOM SNR of [14] is due o is low supply volage which resuls in he smaller oupu swing han ours. V. CONCLUSIONS Fig. 14. Measured oupu volage according o he inpu signal frequency. power is increased from - 18 dbv o - 12 dbv and he THD+N is reduced from - 69.7 db o - 84.9 db. Fig. 13 shows he measured THD+N performance when he inpu signal power is swep from - 100 o 0 dbfs. Fig. 14 show ha he oupu signal ampliude varies wihin A wide-band and low-noise sereo ΔΣ DAC for audio applicaion is proposed. To increase he inpu bandwidh, a half-band FIR filer is designed in he ΔΣ modulaor. The 5 h -order ΔΣ modulaor wih 5-bi quanizer is realized o improve SNR performance. In he analog oupu sage, power efficien DCT-SC DAC is used as an inernal DAC and he opimum curren consumpion is analyzed considering he slew and he linear seling region. The T/H circui wih deglich iming racks he RZ-formaed oupu of he inernal DAC well wih negligible signal loss and harmonic disorions. The 2 nd - order Sallen-Key filer is implemened as a reconsrucion filer. The circui is fabricaed wih 0.13- μm CMOS process which uses he supply volage of 1.2

692 HAN YANG e al : A STEREO AUDIO DELTA-SIGMA DAC WITH 40-kHz BANDWIDTH AND 103-dB SNR V and 3.3 V for digial and analog domain, respecively. The proposed circui achieves 40-kHz inpu bandwidh, 103-dB A-weighed SNR, and - 85-dB THD+N wih a - 12-dBFS inpu signal a 1 khz. REFERENCES [1] Yong-Hee Lee e al., "A 1.3-mW per-channel 103- db SNR sereo audio DAC wih class-d headphones amplifier in 65nm CMOS," 2008 IEEE Symposium on VLSI Circuis, Honolulu, HI, 2008, pp. 176-177. [2] R. Hezar e al., "A 110dB SNR and 0.5mW curren-seering audio DAC implemened in 45nm CMOS," 2010 IEEE Inernaional Solid-Sae Circuis Conference - (ISSCC), San Francisco, CA, 2010, pp. 304-305. [3] H. Weserveld, D. Schinkel and E. van Tuijl, "15.3 A 115dB-DR audio DAC wih 61dBFS ou-ofband noise," 2015 IEEE Inernaional Solid-Sae Circuis Conference - (ISSCC) Diges of Technical Papers, San Francisco, CA, 2015, pp. 1-3. [4] R. C. C. Cheung, K. P. Pun, S. C. L. Yuen, K. H. Tsoi and P. H. W. Leong, "An FPGA-based reconfigurable 24-bi 96kHz sigma-dela audio DAC," Proceedings. 2003 IEEE Inernaional Conference on Field-Programmable Technology (FPT) (IEEE Ca. No.03EX798), Tokyo, Japan, 2003, pp. 110-117. [5] Nikkilä, Seppo. "Inroducing wireless organic digial audio: a mulichannel sreaming audio nework based on IEEE 802.11 sandards." Audio Engineering Sociey Conference: 44h Inernaional Conference: Audio Neworking. Audio Engineering Sociey, 2011. [6] L. Risbo, R. Hezar, B. Kelleci, H. Kiper and M. Fares, "A 108dB-DR 120dB-THD and 0.5Vrms oupu audio DAC wih iner-symbol-inerferenceshaping algorihm in 45nm CMOS," 2011 IEEE Inernaional Solid-Sae Circuis Conference, San Francisco, CA, 2011, pp. 484-485. [7] O. Nys and R. K. Henderson, "A 19-bi low-power mulibi sigma-dela ADC based on daa weighed averaging," in IEEE Journal of Solid-Sae Circuis, vol. 32, no. 7, pp. 933-942, Jul. 1997. [8] R. T. Baird and T. S. Fiez, "Lineariy enhancemen of mulibi ΔΣ A/D and D/A converers using daa weighed averaging," in IEEE Transacions on Circuis and Sysems II: Analog and Digial Signal Processing, vol. 42, no. 12, pp. 753-762, Dec 1995. [9] S. Woo and J. K. Cho, "A Swiched-Capacior Filer Wih Reduced Sensiiviy o Reference Noise for Audio-Band Sigma Dela D/A Converers," in IEEE Transacions on Circuis and Sysems II: Express Briefs, vol. 63, no. 4, pp. 361-365, Apr. 2016. [10] V. Colonna, M. Annovazzi, G. Boarin, G. Gandolfi, F. Sefani and A. Baschiroo, "A 0.22-mm2 7.25- mw per-channel audio sereo-dac wih 97-dB DR and 39-dB SNRou," in IEEE Journal of Solid-Sae Circuis, vol. 40, no. 7, pp. 1491-1498, Jul. 2005. [11] I. Fujimori and T. Sugimoo, "A 1.5 V, 4.1 mw dual-channel audio dela-sigma D/A converer," in IEEE Journal of Solid-Sae Circuis, vol. 33, no. 12, pp. 1863-1870, Dec. 1998. [12] I. Fujimori, A. Nogi and T. Sugimoo, "A mulibi dela-sigma audio DAC wih 120-dB dynamic range," in IEEE Journal of Solid-Sae Circuis, vol. 35, no. 8, pp. 1066-1073, Aug. 2000. [13] J. Yang, X. Wu and J. Zhao, "A RC reconsrucion filer for a 16-bi audio dela-sigma DAC," 2012 IEEE 11h Inernaional Conference on Solid-Sae and Inegraed Circui Technology, Xi'an, 2012, pp. 1-3. [14] Y. h. Lee, M. y. Choi, S. b. You, W. s. Yeum, H. j. Park and J. w. Kim, "A 4mW per-channel 101dB- DR Sereo Audio DAC wih Transformed Quanizaion Srucure," IEEE Cusom Inegraed Circuis Conference 2006, San Jose, CA, 2006, pp. 145-148. [15] Y. Park, H. Yang, H. Kim, J. S. Cho and S. Kim, "Low noise oupu sage for oversampling audio DAC," 2015 28h IEEE Inernaional Sysem-on-Chip Conference (SOCC), Beijing, 2015, pp. 227-230. [16] A. V. Oppenheim and R. W. Schafer, Discree- Time Signal Processing, Englewood Cliffs, NJ, USA: Prenice-Hall, 1989. [17] J. Zhao, X. Wu and M. Zhao, "A digial fron-end of 16-bi audio dela-sigma DAC wih improved CSE mehod and novel DWA," 10h IEEE Inernaional NEWCAS Conference, Monreal, QC, 2012, pp. 273-276. [18] S. Rabii and B. A. Wooley, "A 1.8-V digial-audio sigma-dela modulaor in 0.8-μm CMOS," in IEEE Journal of Solid-Sae Circuis, vol. 32, no. 6, pp. 783-796, Jun. 1997.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.6, DECEMBER, 2018 693 Han Yang received he B.S. and M.S. degrees in he deparmen of elecrical engineering from Seoul Naional Universiy, Seoul, Souh Korea, in 2005 and 2008, respecively. He developed CMOS image sensor readou circuis in Samsung Elecronics from 2008 o 2014. He received he Ph.D. degree in he deparmen of elecrical and compuer engineering from he Seoul Naional Universiy, Seoul, Souh Korea, in 2018. Since Sep. 2018, he has been working CMOS image sensor readou circuis in Samsung Elecronics. His research ineress include ADCs, DACs, and sensor readou circuis. Jun Soo Cho received he B.S. and M.S. degrees in indusrial engineering from Korea Universiy, Seoul, Souh Korea, in 1999 and 2001, respecively, and he Ph.D. degree in elecrical engineering and compuer science from he Seoul Naional Universiy, Seoul, Souh Korea, in 2014. From 2001 o 2014, he was wih Neofideliy, Inc., Seoul Korea and developed audio digial amplifiers and sysems. He is currenly an Indusry-Universiy Collaboraion Professor in Seoul Naional Universiy, Seoul, Souh Korea. His research ineress include low-power, high-resoluion analog and mixed-signal inegraed circuis, including high-fideliy audio ADC and DAC, and relaed sysems. Yujin Park received he B.S. and M.S. degrees in semiconducor science from Dongguk Universiy, Seoul, Korea, in 2003 and 2005, respecively. From 2005 o 2008, he was wih Magnachip Semiconducor, Seoul, Korea. In 2008, he joined Samsung Elecronics and developed CMOS image sensor. He received he Ph.D. degree in he deparmen of elecrical and compuer engineering from he Seoul Naional Universiy, Seoul, Souh Korea, in 2018. His research ineress are in analog and mixed-signal inegraed circuis and sysems. Hyunjong Kim received he B.S. degree in he deparmen of elecrical and compuer engineering from Seoul Naional Universiy, Seoul, Korea, in 2014. He is currenly working owards he Ph.D. degree a he Seoul Naional Universiy, Seoul, Korea. His research ineress are in analog and mixed-signal inegraed circuis and sysems. Suhwan Kim received he B.S. and M.S. degrees in elecrical engineering and compuer science from Korea Universiy, Seoul, Korea, in 1990 and 1992, respecively, and he Ph.D. degree in elecrical engineering and compuer science from he Universiy of Michigan, Ann Arbor MI, in 2001. From 1993 o 1999, he was wih LG Elecronics, Seoul Korea. From 2001 o 2004, he was a Research Saff Member in IBM T. J. Wason Research Cener, Yorkown Heighs NY, USA. In 2004, he joined Seoul Naional Universiy, Seoul, Souh Korea, where he is currenly a Professor of Elecrical and Compuer Engineering. His research ineress include analog and mixed-signal inegraed circuis, high-speed I/O circuis, and silicon-phoonic inegraed circuis. Dr. Kim has received he 1991 Bes Suden Paper Award of he IEEE Korea Secion and he Firs Prize (Operaional Caegory) in he VLSI Design Cones of he 2001 ACM/IEEE Design Auomaion Conference, he Bes Paper Award of he 2009 Korean conference on semiconducors, and he 2011 Bes Paper Award of he Inernaional Symposium on Low-Power Elecronics and Design. He served as a gues edior for he IEEE Journal of Solid-Sae Circuis special issue on he IEEE Asian Solid-Sae Circuis Conference. He has also served as he Organizing Commiee Chair for IEEE Asian Solid Sae Conference and General Co-chair and Technical Program Chair for he IEEE Inernaional Sysem-on-Chip (SoC) Conference. He has paricipaed muliple imes on he Technical Program Commiee of he IEEE Inernaional SOC Conference, he Inernaional Symposium on Low-Power Elecronics and Design, he IEEE Asian Solid-Sae Circuis Conference, and he IEEE Inernaional Solid-Sae Circuis Conference.