FOD00 Single Channel CMOS Optocoupler, FOD0 Dual Channel CMOS Optocoupler Features +V CMOS compatibility ns typical pulse width distortion 0ns max. pulse width distortion 0ns max. propagation delay skew High speed: MBd 0ns max. propagation delay 0kV/µs minimum common mode rejection 0 C to 00 C temperature range UL approved (file #E9000) Applications Line receivers Pulse transformer replacement Output interface to CMOS-LSTTL-TTL Wide bandwidth analog coupling Schematics NC ANODE CATHODE NC FOD00 V DD NC V O GND ANODE CATHODE CATHODE ANODE General Description April 009 The FOD00 and FOD0 optocouplers consist of an AlGaAs LED optically coupled to a high speed transimpedance amplifier and voltage comparator. These optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The devices are housed in a compact -pin SOIC package for optimum mounting density. FOD0 V DD V O V O GND TRUTH TABLE LED OFF ON V O OUTPUT H L Note: A 0.µF bypass capacitor must be connected between pins and. FOD00, FOD0 Rev..0.
Absolute Maximum Ratings (T A = C unless otherwise specified) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units T S Storage Temperature 0 + C T A Ambient Operating Temperature 0 +00 C V DD Supply Voltages 0 Volts V O Output Voltage 0. V DD + 0. Volts I O Average Output Current ma I F Average Forward Input Current 0 ma Lead Solder Temperature 0 C for 0 sec.,. mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section LED Power Dissipation Single Channel Dual Channel Detector Power Dissipation Single Channel Dual Channel Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Electrical Characteristics (T A = 0 C to +00 C) and. V V DD. V *All typicals at T A = C and V DD = V unless otherwise noted. 0mW (derate above 9 C,.mW/ C) 0mW per channel (derate above 90 C,.mW/ C) mw (derate above C,.mW/ C) mw per channel (derate above 90 C,.0mW/ C) Symbol Parameter Min. Max. Units T A Ambient Operating Temperature 0 +00 C V DD Supply Voltages.. Volts I F Input Current (ON) 0 ma Symbol Parameter Test Conditions Min. Typ.* Max. Units Fig. V F Input Forward Voltage I F = ma... V 9 BV R Input Reverse Breakdown Voltage I R = 0µA V V OH Logic High Output Voltage I F = 0, I O = 0µA.0.0 V V OL Logic Low Output Voltage I F = ma, I O = 0µA 0.0 0. V I TH Input Threshold Current (FOD00) (FOD0) I DDL Logic Low Output Supply Current (FOD00) (FOD0) I DDH Logic High Output Supply Current (FOD00) (FOD0) I OL = 0µA.0. I F = ma..9 I F = 0.....0.0.0.0 ma, ma, ma, FOD00, FOD0 Rev..0.
Switching Characteristics Over recommended temperature (T A = 0 C to +00 C) and. V V DD. V. All typical specifications are at T A = C, V DD = + V. Symbol Parameter Test Conditions Min. Typ.* Max. Units t PHL t PLH Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output *All typicals at T A = C and V DD = V unless otherwise noted. Isolation Characteristics (T A = -0 C to +00 C Unless otherwise specified.) *All typical values are at V CC = V, T A = C I F = ma, C L = pf CMOS Signal Levels (Note ) (Fig. 0) I F = ma, C L = pf CMOS Signal Levels, (Note ) (Fig. 0) 0 0 ns FOD00 0 ns FOD0 0 PW Pulse Width 00 ns PWD Pulse Width Distortion I F = ma, C L = pf, 0 0 ns CMOS Signal Levels (Note ) t PSK Propagation Delay Skew I F = ma, C L = pf, CMOS Signal Levels (Note ) 0 ns t R Output Rise Time (0% 90%) I F = ma, C L = pf, CMOS Signal Levels ns t F Output Fall Time (90% 0%) I F = ma, C L = pf, CMOS Signal Levels ns CM H Common Mode Transient Immunity at Logic High Output CM L Common Mode Transient Immunity at Logic Low Output V CM = 000V, T A = C, I F = 0mA, (Note ) (Fig. ) V CM = 000V, T A = C, I F = ma, (Note ) (Fig. ) 0 kv/µs 0 kv/µs Characteristics Test Conditions Symbol Min Typ.* Max Unit Input-Output Insulation Leakage Current Withstand Insulation Test Voltage Relative humidity = %, T A = C, t = s, V I-O = 000 VDC (Note ) I I-O 0µA, R H < 0%, T A = C, t = min. (Note ) I I-O.0 µa V ISO 00 V RMS Resistance (Input to Output) V I-O = 00V (Note ) R I-O 0 Ω Capacitance (Input to Output) f = MHz (Note ) C I-O 0. pf Notes:. Propagation delay time, high to low (t PHL ), is measured from the 0% level on the rising edge of the input pulse to the.v level of the falling edge of the output voltage signal. Propagation delay time, low to high (t PLH ), is measured from the 0% level on the falling edge of the input pulse to the.v level of the rising edge of the output voltage signal.. Pulse width distoration is defined as the absolute difference between the high to low and low to high propagation delay times, t PHL t PLH.. Propagation delay skew, t PSK, is defined as the worst case difference in t PHL or t PLH between units within the recommended operating range of the device.. CM H The maximum tolerated rate of rise of the common mode voltage to ensure the output will remain in the high state, (i,e., V OUT >.0V) Measured in kilovolts per microsecond (kv/µs).. CM L The maximum tolerated rate of fall of the common mode voltage to ensure the output will remain in the low state, (i,e., V OUT < 0.V). Measured in kilovolts per microsecond (kv/µs).. Isolation voltage, V ISO, is an internal device dielectric breakdown rating. For this test, pins,,, are common, and pins,,, are common. FOD00, FOD0 Rev..0.
Typical Performance Curves I TH -Input Threshold Current (ma) I DDL -LogicLow Output Supply Current (ma).0..0..0. V DD =V I OL =0µA Figure. FOD00 Typical Logic Low Output Supply Current vs Ambient Temperature V DD =V I F = ma Figure. FOD00 Typical Input Threshold Current vs Ambient Temperature -0-0 0 0 0 0 0 00 T A -Ambient Temperature ( o C).0-0 -0 0 0 0 0 0 00 T A -AmbientTemperature ( o C) t P -Propagation Delay (ns) I DDH -LogicHighOutput Supply Current (ma) Figure. FOD00 Typical Switching Speed vs Pulse Input Current 00 0 0 0 0 t PHL t PLH PWD 0 9.0..0..0. I F -Pulse Input Current (ma) V DD =V T A = o C Figure. FOD00 Typical Logic High Output Supply Current vs Ambient Temperature V DD =V.0-0 -0 0 0 0 0 0 00 T A -AmbientTemperature ( o C) FOD00, FOD0 Rev..0.
Typical Performance Curves (Continued) I TH -Input Threshold Current (ma) I DDL -LogicLow Output Supply Current (ma)..0..0..0 V DD =V I OL =0µA Figure. FOD0 Typical Logic Low Output Supply Current vs Ambient Temperature V DD =V I F = ma Figure. FOD0 Typical Input Threshold Current vs Ambient Temperature -0-0 0 0 0 0 0 00 T A -Ambient Temperature ( o C). -0-0 0 0 0 0 0 00 T A -AmbientTemperature ( o C) Channel Channel t P -Propagation Delay (ns) I DDH -LogicHighOutput Supply Current (ma) 00 0 0 0 0..0..0..0 Figure. FOD0 Typical Switching Speed vs Pulse Input Current V DD =V T A = o C 0 9 Figure. FOD0 Typical Logic High Output Supply Current vs Ambient Temperature V DD =V t PHL t PLH PWD I F -Pulse Input Current (ma). -0-0 0 0 0 0 0 00 T A -AmbientTemperature ( o C) Channel Channel FOD00, FOD0 Rev..0.
Typical Performance Curves (Continued) I F -Forward Current (ma) Figure 9. Input Forward Current vs. Forward Voltage 00 0 T A =00 o C T A = o C 0. 0.0 T A =-0 o C T A =0 o C T A = o C 0.00 0. 0.9.0....... V F -Forward Voltage (V) FOD00, FOD0 Rev..0.
Pulse Gen. t f = t r = ns Z O = 0 Ω Input Monitor Node I F R IN V FF Test Circuit for FOD00 A B VCM 0V VOH VO I F Vcc Pulse Gen. Z O = 0 Ω t f = t r = ns I F Input 0.µF Monitoring Node Output Monitoring Node R IN Fig. 0 Test Circuit and Waveforms for t PLH, t PHL, t r and t f. GND V CM Pulse Gen V CC Test Circuit for FOD00 0.µF bypass Test Circuit for FOD0 Peak Switching Pos. (A), I = 0 F V O (Min) +V Output (V O) I F V FF Vcc Output Monitoring Node 0.µF Bypass B A Input Output t PHL 90% Dual Channel V CM + Pulse Generator Z O = 0Ω t f Test Circuit for FOD0 0% 0% Waveforms t PLH 0.µF Bypass t r +V Output V O Monitoring Node CM H I F = ma 0% 90%.V CMOS V OL V O (Max) VO VOL Switching Pos. (B), I = ma F CM L Fig. Test Circuit Common Mode Transient Immunity (FOD00 and FOD0) FOD00, FOD0 Rev..0.
Package Dimensions -pin SOIC Surface Mount SEATING PLANE 0. (.) 0. (.) Recommended Pad Layout 0.0 (0.) 0.0 (0.) 0.00 (.) Typ. 0.0 (.) 0. (.) Lead Coplanarity: 0.00 (0.0) MAX 0. (.99) 0. (.9) 0. (.) 0. (.) 0.00 (0.0) 0.00 (0.0) 0.0 (0.) 0.00 (.) 0. (.9) 0. (.9) 0.00 (0.) 0.00 (0.) 0.00 (.) Dimensions in inches (mm). Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ FOD00, FOD0 Rev..0.
Ordering Information Option Order Entry Identifier Description No Suffix FOD00 Shipped in tubes (0 units per tube) R FOD00R Tape and Reel (00 units per reel) Marking Information V X YY 00 Definitions Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option See order entry table) One digit year code, e.g., Two digit work week ranging from 0 to Assembly package code S FOD00, FOD0 Rev..0. 9
Carrier Tape Specification.0 ± 0.0.0 ± 0.0.0 ± 0.0 0.0 MAX.0 ± 0.0. ± 0.0 0. MAX.0 ± 0.0 User Direction of Feed Dimensions in mm Ø. MIN. ± 0.0. ± 0.0.0 ± 0..0 ± 0.0 Ø. ± 0. FOD00, FOD0 Rev..0. 0
Reflow Profile Temperature ( C) 0 0 0 00 0 0 0 0 00 0 0 0 0 0 TP TL Tsmax Tsmin Max. Ramp-up Rate = C/S Max. Ramp-down Rate = C/S Preheat Area 0 0 0 Time C to Peak Time (seconds) Profile Freature Pb-Free Assembly Profile Temperature Min. (Tsmin) 0 C Temperature Max. (Tsmax) 00 C Time (t S ) from (Tsmin to Tsmax) 0 0 seconds Ramp-up Rate (t L to t P ) C/second max. Liquidous Temperature (T L ) C Time (t L ) Maintained Above (T L ) 0 0 seconds Peak Body Package Temperature 0 C +0 C / C Time (t P ) within C of 0 C 0 seconds Ramp-down Rate (T P to T L ) C/second max. Time C to Peak Temperature minutes max. ts tl tp FOD00, FOD0 Rev..0.
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