Ultralow Offset Voltage Dual Op Amp FEATURES Very high dc precision 30 μv maximum offset voltage 0.3 μv/ C maximum offset voltage drift 0.35 μv p-p maximum voltage noise (0. Hz to 0 Hz) 5 million V/V minimum open-loop gain 30 db minimum CMRR 0 db minimum PSRR Matching characteristics 30 μv maximum offset voltage match 0.3 μv/ C maximum offset voltage drift match 30 db minimum CMRR match Available in 8-lead narrow body, PDIP, and hermetic CERDIP and CERDIP/883B packages OUTPUT A PIN CONFIGURATION IN A +IN A V S 3 4 A + 8 +V S 7 OUTPUT B 6 5 IN B +IN B TOP VIEW (Not to Scale) Figure. PDIP (N) and CERDIP (Q) Packages B + 05789-00 GENERAL DESCRIPTION The is a high precision, dual monolithic operational amplifier. Each amplifier individually offers excellent dc precision with maximum offset voltage and offset voltage drift of any dual bipolar op amp. The matching specifications are among the best available in any dual op amp. In addition, the provides 5 V/μV minimum open-loop gain and guaranteed maximum input voltage noise of 350 nv p-p (0. Hz to 0 Hz). All dc specifications show excellent stability over temperature, with offset voltage drift typically 0. μv/ C and input bias current drift of 5 pa/ C maximum. The is available in four performance grades. The J is rated over the commercial temperature range of 0 C to 70 C and is available in a narrow body, PDIP. The A and B are rated over the industrial temperature range of 40 C to +85 C and are available in a CERDIP. The S is rated over the military temperature range of 55 C to +5 C and is available in a CERDIP military version processed to MIL-STD-883B. PRODUCT HIGHLIGHTS. The combination of outstanding matching and individual specifications make the ideal for constructing high gain, precision instrumentation amplifiers.. The low offset voltage drift and low noise of the allow the designer to amplify very small signals without sacrificing overall system performance. 3. The 0 V/μV typical open-loop gain and 40 db common-mode rejection make it ideal for precision applications. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 006 Analog Devices, Inc. All rights reserved.
SPECIFICATIONS @ 5 C and ±5 V dc, unless otherwise noted. Table. J/A B S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE 30 00 5 50 5 30 μv T to T 50 50 5 65 5 50 μv Drift 0.3.0 0. 0.4 0. 0.3 μv/ C Long Term Stability 0.3 0.3 0.3 μv/month INPUT BIAS CURRENT.0.5 0.5.0 0.5 na T to T.0 4.0.0.0.0 4 na Average Drift 5 40 0 5 0 30 pa/ C OFFSET CURRENT VCM = 0 V 0.5.0 0..0 0. na T to T.0 4.0 0..5 0..5 na Average Drift 60 5 5 pa/ C MATCHING CHARACTERISTICS 3 Offset Voltage 80 50 30 μv T to T 50 75 50 μv Offset Voltage Drift.0 0.4 0.3 μv/ C Input Bias Current 4.0.0.0 na T to T 5.0.0.0 na Common-Mode Rejection 0 40 30 40 30 40 db T to T 0 30 30 db Power Supply Rejection 0 0 0 db T to T 0 0 0 db Channel Separation 35 40 40 db INPUT VOLTAGE NOISE 0. Hz to 0 Hz 0.3 0.6 0.3 0.6 0.3 0.35 μv p-p f = 0 Hz 0.3 8 0.3 0.3 nv/ Hz f = 00 Hz 0.0 3.0 0.0.0 0.0 nv/ Hz f = khz 9.6.0 9.6.0 9.6 nv/ Hz INPUT CURRENT NOISE 0. Hz to 0 Hz 4 35 4 35 4 35 pa p-p f = 0 Hz 0.3 0.9 0.3 0.8 0.3 0.8 pa/ Hz f = 00 Hz 0.4 0.7 0.4 0.3 0.4 0.3 pa/ Hz f = khz 0. 0.8 0. 0.7 0. 0.7 pa/ Hz COMMON-MODE REJECTION RATIO VCM = ±3 V 0 40 30 40 30 40 db T to T 0 40 30 40 30 40 db OPEN-LOOP GAIN VO = ±0 V RLOAD kω 3 0 5 0 4 0 V/μV T to T 3 0 5 0 4 7 V/μV POWER SUPPLY REJECTION RATIO VS = ±3 V to ±8 V 0 30 0 30 0 30 db T to T 0 30 0 30 0 30 db FREQUENCY RESPONSE Closed-Loop Bandwidth 0.5 0.9 0.5 0.9 0.5 0.9 MHz Slew Rate 0.5 0.3 0.5 0.3 0.5 0.3 V/μs INPUT RESISTANCE Differential 60 00 00 MΩ Common Mode 00 400 400 GΩ Rev. C Page 3 of 6
J/A B S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit OUTPUT VOLTAGE RLOAD 0 kω 3.5 4 3.5 4.0 3.5 4 ±V RLOAD kω.5 3.0.5 3.0.5 3 ±V RLOAD kω.0.5.0.5.0.5 ±V T to T.0 3.0.0 3.0.0 3 ±V OPEN-LOOP OUTPUT RESISTANCE 60 60 60 Ω POWER SUPPLY Quiescent Current 4.5 5.5 4.5 5.5 4.5 5.5 ma Power Consumption VS = ±5 V 35 65 35 65 35 65 mw VS = ±3 V 8 8 8 mw Operating Range ±3 ±8 ±3 ±8 ±3 ±8 V All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Input offset voltage specifications are guaranteed after five minutes of operation at TA = 5 C. 3 Matching is defined as the difference between parameters of the two amplifiers. Rev. C Page 4 of 6
ABSOLUTE IMUM RATINGS Table. Parameter Rating Supply Voltage ± V Internal Power Dissipation Input Voltage ±VS Output Short-Circuit Duration Indefinite Differential Input Voltage +VS and VS Storage Temperature Range (Q) 65 C to +50 C Storage Temperature Range (N) 65 C to +5 C Lead Temperature (Soldering 60 sec) 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics 8-lead PDIP: θjc = 33 C/W, θja = 00 C/W 8-lead CERDIP: θjc = 30 C/W, θja = 0 C/W For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C Page 5 of 6
OUTLINE DIMENSIONS PIN 0.0 (5.33) 0.50 (3.8) 0.30 (3.30) 0.5 (.9) 0.0 (0.56) 0.08 (0.46) 0.04 (0.36) 0.400 (0.6) 0.365 (9.7) 0.355 (9.0) 8 0.00 (.54) BSC 0.070 (.78) 0.060 (.5) 0.045 (.4) 5 0.80 (7.) 0.50 (6.35) 4 0.40 (6.0) 0.05 (0.38) SEATING 0.005 (0.3) 0.060 (.5) 0.05 (0.38) GAUGE 0.35 (8.6) 0.30 (7.87) 0.300 (7.6) 0.430 (0.9) COMPLIANT TO JEDEC STANDARDS MS-00-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 0.95 (4.95) 0.30 (3.30) 0.5 (.9) 0.04 (0.36) 0.00 (0.5) 0.008 (0.0) 0.00 (5.08) 0.005 (0.3) 0.055 (.40) 0.00 (.54) BSC 0.405 (0.9) 0.00 (5.08) 0.5 (3.8) 0.03 (0.58) 0.04 (0.36) 0.070 (.78) 0.030 (0.76) 8 5 4 0.30 (7.87) 0.0 (5.59) 0.060 (.5) 0.05 (0.38) 0.50 (3.8) SEATING CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 5 0 0.30 (8.3) 0.90 (7.37) Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 0.05 (0.38) 0.008 (0.0) ORDERING GUIDE Model Temperature Range Package Description Package Option JN 0 C to +70 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 JNZ 0 C to +70 C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AQ 40 C to +85 C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 BQ 40 C to +85 C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 SQ/883B 55 C to +5 C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 Z = Pb-free part. Rev. C Page 3 of 6