APPENDIX RFI DESIGN EXAMPLE: MIXER The design of radio frequency integrated circuits (RFIs) is relatively complicated, involving many steps as mentioned in hapter 15, from the design of constituent circuit elements, initial circuit design, analysis and simulation to final circuit design, analysis, simulation and optimization, layout, post-layout simulation and optimization, and final layout. In this appendix, the design of an RFI double-balanced mixer employing a Gilbert cell, which is perhaps one of the most complicated RFIs, is presented as a way to illustrate the design process of RFIs. It is particularly noted that the main objective of the mixer design presented in this appendix is to show a design process for mixers, in particular, and RFIs in general. Attempts are not made to improve the mixer topology or to achieve optimum performance for the circuit. A1.1 IRUIT DESIGN SPEIFIATIONS AND GENERAL DESIGN INFORMATION Table A1.1 shows the design specifications for the mixer. The mixer is designed to generate a 24.5-GHz radio frequency (RF) signal from a 21-GHz intermediate frequency (IF) and 3.5-GHz local oscillator (LO) signals. It is noted that the design specifications for mixers are different for their intended applications. In this design example, the mixer is used as an up-converter to generate an RF signal. Therefore, it is designed to have high linearity, high harmonic and spur rejection, and reasonable noise figure. The mixer is designed using Jazz SB18H2 BiMOS process [1]. The SiGe HBT transistors used in the mixer have a cut-off frequency of 2 GHz, which is well suited for 24.5 GHz operations. The design is carried out using both circuit simulator (adence [2]) and EM simulator (IE3D [3]). Figures obtained from the simulations are shown un-altered to keep the context close to actual designs conducted by RFI designers as much as possible. All on-chip inductors, vias, and interconnects are simulated using IE3D and the resultant S-parameters and/or equivalent-circuit models are imported into adence and used in the mixer design, simulation and optimization. The mixer layout is done using adence. A1.2 MIXER DESIGN Figure A1.1 shows the schematic of the mixer employing a double-balanced Gilbert cell [4]. LO leakage is a critical problem in the mixer design. To lessen this problem, 3.5-GHz is chosen for the LO signal, which Radio-Frequency Integrated-ircuit Engineering, First Edition. am Nguyen. 215 John Wiley & Sons, Inc. Published 215 by John Wiley & Sons, Inc. 83
MIXER DESIGN 831 TABLE A1.1. Mixer Design Specifications IF frequency (GHz) 21 Noise figure (db) < 8 LO frequency (GHz) 3.5 Input 1-dB power compression P in,1db (dbm) > RF frequency (GHz) 24.5 LO power (dbm) < Power conversion gain (db) > 2 LO RF isolation (db) > 4 Side-band Suppression (db) > 4 IF RF isolation (db) > 15 V dd 3pF 25pH 25pH c 3pF 21 GHz IF 6fF 4pH c V b 1 K 2K 12Ω 12Ω 7Ω 7Ω 1 K 2K LO+ c V b 2K c VbM 7Ω 2K LO 7Ω 2K LO+ 2K V b c V 6K 2K 25pH 25pH 6fF 18fF 6K 195pH 195pH 16 ff 16 ff 211fF 2pH 2fF 2fF 414pH 414pH 24.5 GHz RF Input MN Single-ended to differential Double-balanced Gilbert ell Differential to single-ended BPF Figure A1.1. Mixer schematic. is quite far away from the output RF frequency of 24.5 GHz, hence facilitating the removal of the 3.5-GHz LO signal using a low Q band-pass filter (BPF) to improve the purity of the output signal. As shown in Figure A1.1, the mixer consists of an input matching network (MN), (input) single-ended-to-differential active balun, a double-balanced Gilbert cell, an (output) differential-to-single-ended active balun, and a BPF. The input balun is used to accommodate single-ended input IF signals to facilitate on-wafer measurement. The double-balanced Gilbert cell is chosen instead of the single-balanced counterpart to enhance the IF-to-RF and LO-to-RF isolation and even-order suppression. The L tanks at the outputs of the Gilbert cell are used to boost the gain and form band-pass responses. The output balun is used to convert the differential signals at the output of the Gilbert cell to the single-ended RF signals to be used for subsequent single-ended components. This active balun also increases the gain and output power of the mixer, thus also acting as a (differential) amplifier. The BPF passes the 24.5-GHz output signal while suppressing the LO signal, lower-sideband signal at 17.5-GHz, and cross-channel coupling signal at 35 GHz. It is noted that, when used in systems, the mixer should be preceded with a BPF to reject the image signal at 28 GHz. At high frequencies, particularly in the high RF range, the effects of ground pads, vias and interconnects, including vias (even very short ones) used for connecting the transistor terminals from one metal layer to another one, on circuit performance are substantial. It is therefore important to conduct EM simulations for these elements and include the simulated results (e.g., S-parameters) in the circuit simulation. For instance, the vias used for connecting the transistor terminals from Metal 1 or 2 to Metal 6 in the mixer are simulated using IE3D and their S-parameters are included in the transistor s model (i.e., considering these vias as part of the transistor) to take into account the vias effects. It is noted that parasitic components from vias cannot be extracted from the adence RX extraction feature in the current adence version and, hence, EM simulations are the most accurate approach. Figure A1.2 shows the model of the transistors used in the mixer design including the S-parameters of the base, collector and emitter interconnecting vias. Large capacitors () and inductors (L) are used to block the unwanted D and A signals, respectively. It is noted that the post-layout simulation result for the mixer using this model and the EM-simulated S-parameters of other passive components, including interconnects, are more accurate and reliable than the post-layout simulation using the models for the transistors and passive elements from the PDK, and those extracted by the adence RX extraction. The following describes the design of the mixer s constituent components.
832 RFI DESIGN EXAMPLE: MIXER B B E L Base-via [S] ollector-via [S] L Transistor from PDK Emitter-via [S] L E Figure A1.2. Transistor model including S-parameters of interconnecting vias V dd R b2 R c1 R c2 IF IF+ R b3 IF M L M b Q 2 Q 3 R e1 R e2 b V b1 R b1 b Q 1 Figure A1.3. Single-ended to differential active balun. IF is the input, and IF+ and IF are the output. A1.2.1 Single-Ended to Differential Input Active Balun An active balun, as shown in Figure A1.3, is designed to convert a 21-GHz input IF signal from single-ended to differential. It consists of a differential pair (Q 2 and Q 3 ) and a current source (Q 1 ). One input of the differential pair is single-ended and another is grounded through a bypass capacitor. Resistor loads of R c1 and R c2 are used instead of inductors to save the area. The amplitude and phase balance of this input balun is strongly affected by the parasitic capacitors existing at the common node, hence by the size of transistor Q 1 of the current source. Therefore, a trade-off between the amplitude and phase balance and the gain of the input balun is needed. A small size of 6 μm is chosen for transistor Q 1 to obtain a low parasitic capacitance while providing a D current of 6 ma to the differential pair. The input MN, consisting of L M and M,is designed to match the input of the input balun to the 5-Ω source. The values for R c1 and R c2 are chosen so that the D voltage dropped in R c is.6 V, hence providing enough headroom voltages for transistors Q 1, Q 2, and Q 3. Transistors Q 2 and Q 3 are biased at D currents of 3 ma, resulting in highest possible cut-off frequency (f T ) for the transistors. Their sizes are chosen as 3 μm. The degenerative resistors R e1 and R e2 are used to increase the linearity of the input balun. Table A1.2 shows the component values of the input balun. A1.2.2 Double-Balanced Gilbert ell The double-balanced Gilbert mixer cell shown in Figure A1.4 is designed for high gain and linearity, while achieving a reasonable noise figure. It consists of the IF gain stage (Q 5 and Q 6 ), LO switching stage (Q 7,Q 8, Q 9, and Q 1 ), and current source (Q 4 ). The inductors L c1 and L c2 are used to resonate all parasitic capacitors at the outputs of the mixer and form the tuned loads. ompared to using resistor loads, the tuned load boosts
MIXER DESIGN 833 TABLE A1.2. Element Values of the Input Active Balun ircuit element Value Element Value Element Emitter area R c1, R c2 2 Ω b 5pF Q 1.15 6 μm 2 R b1 2kΩ V dd 1.8 V Q 2,Q 3.15 3 μm 2 R b2, R b3 12 kω V b1 1.3 V L M 4 ph M 6 pf V dd L c1 L c2 RF+ R b7 LO+ Q 7 Q 8 IF+ c V b3 R b5 Q 5 R b e3 R b8 RF Q 9 Q 1 LO+ LO Q 6 R e4 R b6 V b3 b IF c V b2 R b4 Q 4 b Figure A1.4. Double-balanced Gilbert mixer. the gain, increases the headroom for transistors, hence increasing the linearity of the mixer, and partly reject the unwanted output frequency components through its band-pass characteristic. As seen in Eq. (13.4), the gain of the mixer is proportional to the transconductance g m of the transistors in the (IF) gain stage and the equivalent resistance R L of the two parallel loading inductors L c1 and L c2.the equivalent load R L can be expressed as R L = QωL c,whereq is the quality factor of the inductor (L c = L c1 = L c2 ). Inductors L c1 and L c2 are designed on the thick topmost metal layer M6 and optimized using IE3D to achieve a high quality factor of 16 which helps improve the gain for the mixer. Large sizes and high bias currents for transistors Q 5 and Q 6 in the IF gain stage are desired for high gain, high linearity, and low noise for the mixer. As there is always a trade-off between the gain and power consumption for mixer design, an iterative optimization is performed to choose proper sizes and bias currents for the transistors. As a result of this analysis, transistors having configuration of one emitter, two base and two collector contacts (BEB) with an emitter area of.15 8 μm 2 are chosen for Q 5 and Q 6.Theyare biased at a current of 6.4 ma for maximum f T. Degenerative resistors R e2 of 1 Ω are used to further improve the linearity of the IF stage. Since the noise contribution of the mixer mainly comes from the IF stage as long as the transistors in the LO stage are switched abruptly, large-size Q 5 and Q 6 having two base contacts would lower the thermal noise contribution due to small base resistors. Transistor Q 4 in the current source has a size of.15 1 μm 2 and is biased at 12.8 ma to provide sufficient current for the mixer cell. The small size of Q 4 results in small parasitic capacitance and hence increasing the common-mode rejection for the mixer. Thesizesofthetransistors(Q 7,Q 8,Q 9, and Q 1 ) in the LO switching stage are chosen to be small with multibase and collector configuration for fast switching. Smaller-size transistors result in lower LO power needed at an expense of lower linearity due to lower current-handling capability. Fast switching for the LO switching stage results in improved linearity and reduced noise contribution from the LO switching transistors. Simulations show that a transistor size of.15 4 μm 2 gives lowest noise figure with a low LO power of 4 dbm. All the bypass capacitors b s have values of 5 pf. The coupling capacitors c s in the IF stage are 2 ff. The mixer core consumes a 12.8-mA D current from a supply voltage of 1.8 V.
834 RFI DESIGN EXAMPLE: MIXER TABLE A1.3. ircuit Element Values of the Gilbert Mixer ell Element Value Element Value Transistor Emitter area L c1 25 Ω c 2 ff Q 4.15 1 μm 2 R b3, R b4 2kΩ V dd 1.8 V Q 5,Q 6.15 8 μm 2 R b5 1kΩ R e2 1 Ω Q 7,Q 8,Q 9,Q 1.15 4 μm 2 V dd RF+ c3 RF c4 R L b1 c3 L c4 R b1 c6 1 c5 RF Q 12 Q 13 L e1 L e2 V b4 R b9 b Q 11 Figure A1.5. Differential to single-ended active balun. RF+ and RF are the input and RF is the output. Table A1.3 summarizes the values of the elements used in the Gilbert mixer cell. A1.2.3 Differential to Single-Ended Output Active Balun A differential to single-ended active balun, as shown in Figure A1.5, is used at the output of the mixer core to convert differential to single-ended signals, as well as to increase the mixer s conversion gain and output power. It functions indeed as a differential amplifier. Transistors Q 12 and Q 13 are designed with a large emitter area of.15 8 μm 2 and biased at a D current of 7 ma for high gain and linearity. Transistor Q 11 biased at 14 ma functions as a D current source for this output balun. The load inductors L c3 and L c4 are optimized to tune all the parasitic capacitors at the collectors of Q 12 and Q 13, as well as form the L tanks for signal selectivity and side-band and LO suppression. L c3,l c4 are also used with capacitor c3 to form a current combiner functioning as a passive balun to convert the differential signal to single-ended signal. apacitors c3, c4, and c6 are used to provide the matching at the input and output of the output balun, respectively. Degenerative inductors L e1 and L e2 are used to increase the linearity of the output balun. There is a trade-off between the gain and linearity of the output balun due to values of the degenerative inductors. The values of L e1 and L e2 are chosen to be 25 ph through several iterations. These inductors are implemented using simple metal traces (lines). The values of the elements used in the output balun are shown in Table A1.4. A1.2.4 Band-Pass Filter Figure A1.6 shows the schematic of the BPF used at the output of the differential to single-ended output active balun to select the 24.5-GHz RF signal and suppress the lower sideband at 17.5 GHz and the cross channel TABLE A1.4. ircuit Element Values of the Output Active Balun Element Value Element Value Transistor Emitter area L c3, L c4 25 Ω c3, c4 2 ff Q 11.15 1 μm 2 R b1, R b11 6KΩ 5 6 ff Q 12,Q 13.15 8 μm 2 R b9 2KΩ L e1, L e2 25 ph V dd 1.8 V
MIXER OPTIMIZATION AND LAYOUT 835 195 ph 195 ph In 16 ff 16 ff 211 ff 2 ph 2 ff 2 ff Out 414 ph 414 ph Figure A1.6. Band-pass filter. leakage at 35 GHz. Simulation results show that the BPF exhibits an insertion loss of 1.8 db at 24.5 GHz and rejection of 34 and 37 db at 17.5 and 35 GHz, respectively. A1.3 MIXER OPTIMIZATION AND LAYOUT The design of mixers at high frequencies in the RF regime is not straight forward as there are many trade-off parameters in the design and EM effects resulting from layouts. Mixer design, hence, requires various iterative optimization and layout and, in general, is performed in three stages: initial, intermediate, and final stages. In the initial design, ideal resistors, capacitors, and inductors as well as transistors from the PDK of the employed process can be used to design and optimize the mixer to meet its required specifications. Optimization of the mixer requires understanding of trade-off between the mixer parameters including gain, linearity, noise figure, power consumption, LO power level, and actual implementation of passive components (which affect the chip area). In the intermediate design stage, after the optimization of the mixer using ideal components and transistor models from the PDK in the initial design, the transistors are replaced with the model described in Figure A1.2, the designed ideal capacitors are replaced with real capacitors from the PDK, and the designed idealinductorsarereplacedby their S-parameters obtained from the EM simulated design. As expected, the performance of the resultant mixer circuit is normally different from that of the mixer based on ideal components in the initial design. Therefore, further optimization is needed for the mixer to meet the required specifications. A layout for the mixer is then prepared. In the final design stage, the interconnects resulting from the mixer layout are modeled accurately using IE3D and included in the mixer simulation. This step, requiring the use of EM simulators, is important for the mixer design. During the layout process, some already designed components, particularly inductors, may need to be modified due to constraints in the layout. The altered components then need to be simulated using an EM simulator and included in the mixer simulation. Further optimization of the mixer may be needed. ompletion of the mixer design is done in an interactive way, requiring several iterations going back and forth among the layout and EM and circuit simulations. During this process, the mixer layout also needs to be optimized to improve the mixer performance by various ways, such as reduction of parasitics, better layout symmetry, etc. Figure A1.7 shows the final layout of the entire mixer. The layout is done as symmetrical as possible in order to preserve the symmetry needed for the Gilbert mixer core to work properly. The size of the whole mixer is around 1.2 mm.9 mm, while that of the mixer core is about 6 μm 35 μm. As can been seen, most of the chip area is occupied by the passive components (mainly inductors and interconnects). Metal 6 (the topmost metal layer) is used for the IF, LO, and RF signals. A robust ground consisting of six stacked metal layers is placed around the mixer. Metal 5 and metal 6 are used for the interconnects at the LO and RF port. Poly blocking layers are inserted underneath all the inductors to prevent the poly dummies added during fabrication from affecting the inductor performance.
836 RFI DESIGN EXAMPLE: MIXER Figure A1.7. Mixer layout. Kf B1f 8 1.25 6 1. Y (E3) 4 Y.75.5 2.25 1 2 3 4 5 6 7 8 Frequency (GHz) (a) 1 2 3 4 5 6 7 8 32.29 GHz.63815 Frequency (GHz) (b) Figure A1.8. Mixer s stability factors K (a) and B1 (b). Input power is 4 dbm. A1.4 SIMULATION RESULTS A1.4.1 Stability Stability is an important issue and should be the first to check in the mixer design. Stability can be evaluated using S-parameter simulation with the LO port terminated. When the LO port is terminated, the mixer can be considered a two-port amplifier with the IF and RF ports being the input and output ports, respectively, and its stability is checked as an amplifier. Simulations done in adence with different loads for the LO port show that the mixer is unconditionally stable from D to 8 GHz. Figure A1.8 shows the results with the LO port shorted, showing that the mixer s stability factors K and B 1 given in Eq. (1.4) are larger than 1 and, respectively. A1.4.2 Return Loss Figure A1.9 shows the simulated input (IF) and output (RF) return losses of the mixer. The input and output return losses are more than 22 and 1 db at the IF and RF frequencies of 21 and 24.5 GHz, respectively. A1.4.3 onversion Gain The mixer s conversion gain versus LO power is simulated using the harmonic-balance tool available in adence to determine the optimum LO power that provides maximum gain. The input IF signal is 4 dbm at 21 GHz. The LO signal is fixed at 3.5 GHz and its power is swept from 1 to 3 dbm in 1-dBm steps. The conversion gain is calculated as the ratio of the 24.5-GHz RF output power and 21-GHz IF input power. Figure A1.1(a) shows the simulated conversion gains versus LO power. The results show that a maximum
SIMULATION RESULTS 837 S 22 db2 5. S 11 db2 Output RL 5. Y (db) 1 15 2 Input RL 25 1 2 3 29.73 GHz 8.572 db Frequency (GHz) 4 Figure A1.9. Mixer s input (IF) and output (RF) return loss (RL). Gain Gain 25.5 27.5 Gain () 25.25 25. 24.75 24.5 24.25 24. 23.75 Gain () 25. 22.5 2. 17.5 15. 12.5 23.5 1. 1. 7.5 5. 2.5 16. 18. 2. 22. 9.637 23.9134 PLO () 2.2596E1 23.854 FRF (E9) (a) (b) 24. 26. Figure A1.1. Mixer s conversion gain versus LO power (a) and IF frequency (b). gain of 25.3 db is obtained for the mixer with an LO power of 4 dbm. This LO power is used for other simulations. The small LO power is achieved by using small-size transistors in the LO stage. The simulation for the mixer s conversion gain versus IF frequency is carried out using the harmonicbalance analysis to characterize the frequency response o the mixer with respect to the IF frequency. The IF power is set at 4 dbm and the IF frequency is swept from 16 to 26 GHz. The LO frequency and power are fixed at 3.5 GHz and 4 dbm, respectively. Figure A1.1(b) shows the simulated conversion gains versus IF frequency. As can be seen, the mixer exhibits a maximum gain of 25.5 db at an IF frequency of 21 GHz. A1.4.4 Noise Figure Figure A1.11 shows the simulated noise figure of the complete mixer versus the input IF frequency using the harmonic-balance analysis. The LO frequency and power are set at 3.5 GHz and 4 dbm, respectively, and the IF signal at 4 dbm is swept from 15 to 3 GHz. At 21 GHz, the noise figure is 7.6 db which, although not very good, is a reasonable value for the mixer used as an up-converter and meets the design requirement for the noise figure. A1.4.5 Other Mixer Performance Figure A1.12 shows the simulated gain, RF output power (at 24.5 GHz), IF-to-RF isolation, LO-to-RF isolation, and lower-sideband suppression versus the IF input power. In these simulations, the LO frequency and
838 RFI DESIGN EXAMPLE: MIXER 14 13 12 NF() 11 1 9. 8. 7. 15. 17.5 2. 22.5 25. 27.5 2.159E1 7.577 Frequency (GHz) (E9) Figure A1.11. Mixer s noise figure versus IF frequency. 5. Output power (dbm), gain, and isolation (db) () 25. 25. 5. 75. Gain Low side band rejection LO RF isolation RF output power (dbm) IF RF isolation 1 4 35 3 25 2 15 1 24. 75.39 IF power (dbm) () Figure A1.12. Mixer s gain, output power, isolation and lower-sideband suppression. power are fixed at 3.5 GHz and 4 dbm, respectively, and the IF signal is set at 21 GHz, while its power is swept from 4 to 1 dbm. The simulation results show that the mixer exhibits a maximum gain of 25.3 db, 1-dB output power compression (P out-1 db) of 1.28 dbm, lower-sideband suppression of 56 db, IF RF isolation higher than 17 db, and LO RF isolation more than 6 db. Figure A1.13 displays the output signal spectrum of the mixer with 3.5-GHz LO signal of 4-dBm and 21-GHz IF signal of 23 dbm. The spectrum shows a 24.5-GHz RF tone with power of 1.28 dbm and harmonic and inter-modulation products suppressed by more than 25 db from the 24.5-GHz signal. By changing the bias voltage V b2 of the Gilbert cell, indicated in Figure A1.4, from.78 to 1.3 V, the gain of the mixer changes from 1 to +25.3 db, which signifies that the designed mixer can work as a variable-gain mixer with a substantial gain-tuning range. The performance of the mixer is summarized and compared with the design specifications in Table A1.5. It shows that the designed mixer meets the required specifications. A1.5 MEASURED RESULTS Figure A1.14 shows the mixer fabricated on the Jazz SB18H2 BiMOS process. The fabricated mixer was measured on-wafer using a Rhode & Schwarz vector network analyzer and ascade probe station. The short-open-load-thru calibration method along with Microtech s impedance standard substrate standards
MEASURED RESULTS 839 TABLE A1.5. Simulated Performance versus Specifications Parameter Design specification Simulated results IF frequency (GHz) 21 21 LO frequency (GHz) 3.5 3.5 RF frequency (GHz) 24.5 24.5 Power conversion gain (db) 2 25.3 Side-band suppression (db) 4 56 Noise figure (db) 8 7.6 P in,1db (dbm) > 1.28 LO power (dbm) < 4 LO RF isolation (db) >4 6 IF RF isolation (db) >15 17 1. 24.5 GHz 1.28 dbm 1. Output power (dbm) 2. 3. 4. 5. 2 4 6 24.5 GHz 1.2841 db Frequency (GHz) Figure A1.13. Mixer s output spectrum. Figure A1.14. Mixer s microphotograph. was used. The mixer s stability was first confirmed by calculating the stability factors K (> 1) and B 1 (> ) using the measured S-parameters. The mixer consumes a current of 4 ma from a power supply of 1.8 V. The measured and simulated results agree reasonably well, validating our design. Some of the measured results are described as follows. Figure A1.15 shows the simulated and measured input and output return losses versus IF and RF frequencies. Figure A1.16 shows the simulated and measured conversion gain and output power versus IF input
84 RFI DESIGN EXAMPLE: MIXER Output return loss Input and output return loss (db) 5 1 15 Input return loss 2 Measured Simulated 25 5 1 15 2 25 3 35 4 45 5 Frequency (GHz) Figure A1.15. Simulated and measured input and output return losses of mixer. onversion gain (db) and output power (dbm) 3 2 1 1 2 4 onversion gain 35 RF output power 3 25 2 IF input power (dbm) Measured Simulated 15 1 Figure A1.16. Simulated and measured conversion gain and output power of mixer. power, where the LO frequency and power are fixed at 3.5 GHz and 2 dbm, respectively, while the IF frequency is set to 21 GHz. REFERENES 1. Jazz Semiconductor, 4321 Jamboree Road, Newport Beach, A 9266. 2. adence Design Systems, Inc., 2655 Seely Avenue, San Jose, A 95134. 3. IE3D, Zeland Software, Inc., Fremont, A, 94538. 4. B. Gilbert, A Precise Four-Quadrant Multiplier with Subnanosecond Response, IEEE J. Solid-State ircuits, Vol. 3, pp. 365 373, Dec. 1968.