Common mode rejection ratio Definition: Common mode rejection ratio represents the ratio of the differential voltage gaina d tothecommonmodevoltagegain,a cm :
Common mode rejection ratio Definition: Common mode rejection ratio represents the ratio of the differential voltage gain A d to the commonmodevoltagegain,a cm : Ad Vicm CM Ac V Meaning: CM represents the measure of the fluctuation of input offset, Vio, caused by the changes of the DC input voltage, Vicm. CM describes how well an operational amplifier rejects variations in input common mode voltage Vicm. Cause: Fluctuation of the DC input voltage cause changes in the bias point of the differential pair input transistors. These changes in the bias point affects input voltage offset. io 2
Power Supply ejection atio PS Definition: Power Supply ejection atio(ps) is the ratio of the change in power supply voltages to the corresponding change in the input offset voltage. ( VCC VEE) PS V io Meaning: PS represents the measure of the fluctuation of input offset voltage, Vio, caused by the changes of the power supply voltage VCC. It describes the capability of an op-amp to suppress any power supply variations Cause: Fluctuations in the power supply, VCC, cause changes in the bias point of the differential pair input transistors. These changes in the bias point affects input voltage offset, Vio.
Power Supply ejection atio PS In this example, a 0mV, 00kHz signal is superimposed on the power supply (Vs 5V ±0mV). The power supply noise is attenuated by 45dB PS at 00kHz and reflects as an input offset voltage variation. Notice that the output has the power supply noise and the input signal superimposed on each other. V G CL V out out V 2 os G V CL os Vs PS Vs 0mV PS 78 2 5,6mV 56µ V Input offset voltage caused by power supply nose, Vos power supply nose, Vs
PS and CM PS V V d SS V PS log Vd SS 20 About 90dB CM A d Ac V V icm io CM20log A d Ac
Input resistance Differential input, id, is measured as the ratio of the voltage and current of a voltage source connected between opamp inputs. Common mode input resistance, ic, is measured between shorted inputs and ground. v id i in d v ic i in CM 6
Input impedance Both inputs have parasitic impedance associated with them. Figure shows a model of the resistance and capacitance between each input terminal and ground and between the two terminals. Input resistance, iis the resistance between the input terminals with other input grounded. Its value is between 0 7 and0 2 Ω. Input capacitance, Ci, is measured between the input terminals with either input grounded. Ciis usually a few pf. ( + ) id ic d n n p p
Input resistance As a consequence of the negative feedback input resistance increases. Input impedance of a non-inverting amplifier circuit is approximately equal to the product of the input Op-amp input impedance and desensitivity factor (+Aβ). i v i x vx v id v0 v0 A β + β ( v ) x v 2 x v x id A β v + A β id in + ( Aβ) x
Output impedance Typical values for the output impedance are between 0Ω and 00Ω. Iftheloadiscapacitive,theextraphaseshiftwilleffectthephasemargin. ail-to-rail output op amps use a common emitter (bipolar) or common source (CMOS) output stage. They have higher output impedance than emitter follower output stages. V 0 AV in L L + 0 V 0 AV in ω + j ω 0 ω 0 0 C L
Output impedance As a consequence of the negative feedback output impedance decreases. The output impedance of the inverting and non-inverting amplifier can be obtained as the ratio of the op-amp output resistance and desensitivity factor(+aβ).. 2 0 v Av v i x ID x x + + v x v x v + β 2 0 2 0 A A v i x x out β β + + + +
Slew rate Definition: Slew rate, S, is the rate of changeintheoutputvoltagecausedbyastep input signal. dv S o dt [ V/µs] Cause: Output voltage change is limited by the charging and discharging of the internal capacitor, which is added to make the op amp unity gain stable. The maximum rate of change occurs when on one of the differential pair transistors goes to cut off state. Consequence: Cause nonlinear distortion whenever the slop of the input signal is higher than slew-rate.
Slew rate Step response of a linear system without slew rate is exponential and its slope depends on final output value. Due to the a limited current that charge internal capacity step response displays a linear ramp and have constant slope. The slope of ramp is the slew rate.
Slew rate lllllllllllllll lllllllllllllll lllllllllllllll l The analysis of Slew-ate is a large-signal analysis, therefore we will consider large swings of the input signal. In this case, the left side of the differential pair is conducting all the tail current IT and mirroring to the other side through the PMOS current mirror. Capacitor CC charges at a rate: dv S max dt I C T c
Slew rate Slew rate enables us to estimate which frequency of signal can be applied without distortion. The maximum slope of the input sine wave signal depends on its amplitude and frequency dv v dt in out ( t) V sin( ωt) dv out dt inm ω + f p max S 2πV 2 Vinmcos( ωt) ω Voutmcos( ωt) V ω< S outm outm
3. Day. problem Designanintegratorforaunitygainfrequency0MHzandinput impedance of 2 kω. If operational amplifier provides a slew rate of 0, V/ns what is the largest peak-to-peak sinusoidal swing at the inputatmhzthatop-ampcanoutputwithoutslewing?
Maximum Output Voltage Swing The output can't swing all the way to the power supply rails. The max output voltage also depends on the load current. With a smaller load (i.e. a big load resistor drawing little current) the output can go higher than with a large load (i.e. a small load resistor requiring more current). Most Op-amps can swing the output to within a few volts of the power supply rails. Most op-amps can swing the output to within a few volts of the power supply rails. 6
Maximum Output Voltage Swing Amplifier in class B
Maximum Output Voltage Swing The maximum output voltage, VOM±, is defined as the maximum positive or negative peak output voltage that can be obtained without wave form clipping, when quiescent DC output voltage is zero.
Output Short Circuit Current The maximum continuous output current available from the amplifier with the output shorted to ground, or a supply. During the negative half cycle I OUT <0. transistor Q goes to cut off state when I OUT I Q where:i Q isthecurrentofthecurrentsink, Qisthetransistoroftheoutputstage
3. Day 2. Problem Inanon-invertingamplifier,asshowninfigure,itisgiven:v in (t)v in sinωt; V in 5V; kω; 2 3 kω. The current that op-amp can supplytoaloadislimittedtoi Omax +-25mA;powersupplyvoltage isv CC 2V.Findtheoutputvoltageintimedomainif: a) L 0 kω; b) L 00Ω;
3. Day 3. Problem Design an inverting amplifier with input impedance of 00 Ω and gain of A n -5. We have an op-amp with open-loop DC gain of A 0 0 4, power supply voltage of 2 V, output short circuit current of I Omax ±5 ma. Calculate the maximum input signal which can be amplified without distortion.