PD - 9733 Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability G D S V DSS R DS(on) typ. max. I D D IRFR386PbF IRFU386PbF HEXFET Power MOSFET G S 6V 2.6mΩ 5.8mΩ 43A G DS D-Pak IRFR386PbF I-Pak IRFU386PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, VGS @ V 43 I D @ T C = C Continuous Drain Current, V GS @ V 3 A I DM Pulsed Drain Current c 7 P D @T C = 25 C Maximum Power Dissipation 7 W Linear Derating Factor.47 W/ C V GS Gate-to-Source Voltage ± 2 V dv/dt Peak Diode Recovery e 24 V/ns T J Operating Junction and -55 to 75 C T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) 3 Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy d 73 mj I AR Avalanche Current c 25 A E AR Repetitive Avalanche Energy f 7. mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case j 2.2 R θcs Case-to-Sink, Flat Greased Surface.5 C/W R θja Junction-to-Ambient ij 62 www.irf.com 3/4/8
IRFR/U386PbF Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage 6 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.75 V/ C Reference to 25 C, I D = 5mAc R DS(on) Static Drain-to-Source On-Resistance 2.6 5.8 mω V GS = V, I D = 25A f V GS(th) Gate Threshold Voltage 2. 4. V V DS = V GS, I D = 5µA I DSS Drain-to-Source Leakage Current 2 µa V DS = 6V, V GS = V 25 V DS = 48V, V GS = V, I GSS Gate-to-Source Forward Leakage na V GS = 2V Gate-to-Source Reverse Leakage - V GS = -2V Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 4 S Q g Total Gate Charge 22 3 nc Q gs Gate-to-Source Charge 5. Q gd Gate-to-Drain ("Miller") Charge 6.3 Q sync Total Gate Charge Sync. (Q g - Q gd ) 28.3 R G(int) Internal Gate Resistance.79 Ω t d(on) Turn-On Delay Time 6.3 ns t r Rise Time 4 t d(off) Turn-Off Delay Time 49 t f Fall Time 47 C iss Input Capacitance 5 C oss Output Capacitance 3 C rss Reverse Transfer Capacitance 67 pf C oss eff. (ER) Effective Output Capacitance (Energy Related)h 9 C oss eff. (TR) Effective Output Capacitance (Time Related)g 23 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 43 A Conditions V GS = V, I D = 25µA Conditions V DS = V, I D = 25A I D = 25A V DS = 3V V GS = V f I D = 25A, V DS =V, V GS = V V DD = 39V I D = 25A R G = 2Ω V GS = V f V GS = V V DS = 5V ƒ =.MHz V GS = V, V DS = V to 6V h V GS = V, V DS = V to 6V g Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 7 integral reverse G S (Body Diode)c p-n junction diode. V SD Diode Forward Voltage.3 V, I S = 25A, V GS = V f t rr Reverse Recovery Time 22 33 ns V R = 5V, 26 39 I F = 25A Q rr Reverse Recovery Charge 7 26 nc di/dt = A/µs f 24 36 I RRM Reverse Recovery Current.4 A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) D Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by T Jmax, starting, L =.23mH R G = 25Ω, I AS = 25A, V GS =V. Part not recommended for use above this value. ƒ I SD 25A, di/dt 58A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. When mounted on " square PCB (FR-4 or G- Material). For recom mended footprint and soldering techniques refer to application note #AN-994. ˆ R θ is measured at T J approximately 9 C. 2 www.irf.com
C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRFR/U386PbF VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V 4.5V 4.5V 6µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 6µs PULSE WIDTH Tj = 75 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.5 I D = 25A V GS = V 2. T J = 75 C.5. V DS = 25V 6µs PULSE WIDTH 2 3 4 5 6 7 8 9 V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics.5-6 -4-2 2 4 6 8 2468 T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss 2.. 8. I D = 25A V DS = 48V V DS = 3V V DS = 2V C oss 6. C rss 4. 2.. 5 5 2 25 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRFR/U386PbF OPERATION IN THIS AREA LIMITED BY R DS (on) µsec T J = 75 C msec msec V GS = V..5..5 2. V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Tc = 25 C Tj = 75 C DC Single Pulse V DS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 45 4 8 Id = 5mA 35 3 25 2 5 5 75 7 65 25 5 75 25 5 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 6-6 -4-2 2 4 6 8 2468 T J, Temperature ( C ) Fig. Drain-to-Source Breakdown Voltage.4.3.3 3 25 2 I D TOP 2.8A 5.A BOTTOM 25A.2.2 5 5. - 2 3 4 5 6 7 25 5 75 25 5 75 Starting T V DS, Drain-to-Source Voltage (V) J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) IRFR/U386PbF D =.5 Thermal Response ( Z thjc ) C/W..2..5.2. R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci τi/ri Notes: SINGLE PULSE. Duty Factor D = t/t2 ( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc Tc. E-6 E-5... t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case τ C τ Ri ( C/W) τi (sec).686.26.9926.228.523.82.5. Duty Cycle = Single Pulse. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 5 C..E-6.E-5.E-4.E-3.E-2.E- tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth 8 6 4 2 TOP Single Pulse BOTTOM.% Duty Cycle I D = 25A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR (A) I RR (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RR (A) IRFR/U386PbF 4. 3.5 3. 4 2 I F = 7A V R = 5V 2.5 2. I D = 5µA I D = 25µA I D =.ma I D =.A 8 6 4.5 2. -75-5 -25 25 5 75 25 5 75 2 T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 4 6 8 di F /dt (A/µs) Fig. 7 - Typical Recovery Current vs. di f /dt 4 2 I F = 25A V R = 5V 26 2 I F = 7A V R = 5V 8 6 6 4 2 6 2 4 6 8 2 4 6 8 di F /dt (A/µs) di F /dt (A/µs) Fig. 8 - Typical Recovery Current vs. di f /dt Fig. 9 - Typical Stored Charge vs. di f /dt 26 2 6 I F = 25A V R = 5V 6 2 4 6 8 di F /dt (A/µs) Fig. 2 - Typical Stored Charge vs. di f /dt 6 www.irf.com
IRFR/U386PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T I AS.Ω - V DD A I AS Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms L D V DS V DD - V DS 9% D.U.T % V GS Pulse Width < µs Duty Factor < % V GS t d(on) t r t d(off) t f Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms Vds Id Vgs K DUT L VCC Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform www.irf.com 7
IRFR/U386PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information (;$3/( 7,6,6$,5)5 :,7$66(%/< $66(%/('2::,7($66(%/</,($,7(5$7,2$/ 5(&7,),(5 /2*2,5)5 $ 3$578%(5 '$7(&2'( <($5 :((. RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH $66(%/< /,($ 3LQDVVHPEO\OLQHSRVLWLRQLQGLFDWHV /HDG)UHHTXDOLILFDWLRQWRWKHFRQVXPHUOHYHO 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/<,5)5 3$578%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ 3 '(6,*$7(6/($')5(( 352'8&748$/,),('727( &268(5/(9(/237,2$/ <($5 :((. $ $66(%/<6,7(&2'( Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com
IRFR/U386PbF I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-25AA) Part Marking Information (;$3/( 7,6,6$,5)8 :,7$66(%/< $66(%/('2::,7($66(%/</,($ RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/<,5)8 $ 3$578%(5 '$7(&2'( <($5 :((. /,($ 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/<,5)8 3$578%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(%/<6,7(&2'( Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRFR/U386PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 252-75 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information. 3/8 www.irf.com