FPGA-Based Autonomous Obstacle Avoidance Robot.

People s Democratic Republic of Algeria Ministry of Higher Education and Scientific Research University M Hamed BOUGARA Boumerdes Institute of Electrical and Electronic Engineering Department of Electronics Final Year Project Report Presented in Partial Fulfilment of the Requirements for the Degree of MASTER In Electrical and Electronic Engineering Option: Computer Engineering. Title: FPGA-Based Autonomous Obstacle Avoidance Robot. Presented by: - AZZOUGUI Yasmina. - MAKHLOUF Yasmine. Supervisor: Dr.BENZEKRI Registration Number:.../2015

Dedication We would like to thank our families, for their encouragement and support. We owe all our success to them. I

Acknowledgement We would like to thank our supervisor Dr. A. Benzekri for his support during the completion of the project. We would like also to extend our deepest gratitude to Mrs.Gouda for her guidance, and all the teachers who encouraged us and supported us during our work. II

Abstract The aim of this report is to describe the design and the implementation of a Field Programmable Gate Array (FPGA)-Based autonomous obstacle avoidance robot. The rotating sonar system mounted on a servo motor performs the obstacle detection, by reading obstacle distances at known angles, with respect to the center of the robot. The digital controller is designed using a heterogeneous computer platform, this platform consists of the System on Programmable Chip (SoPC) that reads data from the sensor, and a custom hardware developed in both Very high speed integrated circuit Hardware Description Language (VHDL) and Library of Parallel Modules (LPMs). After processing data and taking decisions, the obstacle avoidance task is performed by generating Pulse Width Modulation (PWM) signals to actuate the direction of the wheels. The system is developed using the Altera Quartus II software web edition version 9.1, and realized on a Cyclone-II EP2C35F672 lowcost FPGA platform to verify its feasibility and functionality. III

Table of contents Dedication.... Acknowledgement Abstract... I II III Table of contents... IV List of Acronyms... List of Figures... VII VIII Chapter 1 Introduction 1.1. Overview.. 01 1.2. Motivation 01 1.3. Objective.. 02 1.4. Structure of the System... 02 1.5. Organization of the Report... 05 Chapter 2 Theoretical Background 2.1. Field Programmable Gate Array. 06 2.1.1. Applications. 06 2.1.2. The DE2 Development and Education Board.. 06 2.1.3. Soft Core Processors 07 Nios II Processor. 07 2.1.4. System on Programmable Chip SOPC... 08 2.2. The Robot 09 2.3. Micro Servo Sg90... 10 2.4. Ultrasonic Sensor 10 IV

2.5. H- Bridge... 11 2.6. Software and Hardware Tools.. 13 Chapter 3 Hardware System Design 3.1. Introduction. 14 3.2. Off chip Hardware Design 15 3.2.1. Sensing Unit and its Support 15 Ultrasonic Sensor. 15 Servo Motor.. 16 3.2.2. Motor Driving Unit 17 H-Bridge.. 17 Protective Circuit.. 17 3.2.3. Bidirectional Voltage Translation 18 3.3. On Chip System Design 18 3.3.1. SoPC System 18 3.3.2. Non-SoPC System 20 Sensor Trigger Signal Generator.. 20 Servo Motor PWM Generator.. 21 DC Motor Direction Control Unit 21 DC Motor PWM Generator. 22 Chapter 4 Software System Design 4.1. Introduction. 26 4.2. Main Program. 26 4.3. Scanning Procedure. 27 4.4. Obstacle Detection.. 28 V

4.5. Obstacle Avoidance 29 4.6. Examples. 30 4.7. Programming Language.. 32 Chapter 5 Conclusion Conclusion 34 References.. 35 Bibliography. 36 VI

List of Acronyms.bdf: block diagram file..bsf: block schematic file. ADC: Analog to Digital Converter. ASIC: application specific integrated circuit. DE2 board: Development and Education board. DSP: Digital Signal Processing. FPGA : Field Programmable Gate Array. GUI: Graphical User Interface. I/O: Input Output. IC: Integrated Circuit. IDE: Integrated Development Environment. JP1: Jumper 1. JTAG: Joint Test Action Group. LPM: Library of Parallel Modules. PLL: Phase-Locked Loop. PWM: Pulse Width Modulator. RAM: Random Access Memory. RISC: Reduced Instruction Set Computer. ROM: Read Only Memory. RTL: Register Transfer Level. SDRAM: Synchronous Dynamic Random Access Memory. SoPC: System on Programmable Chip. SPI: Serial Peripheral Interface. SRAM: Static Random Access Memory. UART: Universal Asynchronous Receiver Transmitter VHDL: Very high speed integrated circuit Hardware Description Language. VII

List of Figures Figure 1.1 Figure1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 Figure 2.10 Figure 2.11 Figure 2.12 Figure 2.13 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure3.11 Figure3.12 Figure 3.13 First Digitally Operated and Programmable Robot (Unimate)...1 Microprocessor Based System..2 Example of a Microcontroller Chip...3 Altera FPGA Chip...3 General Block Diagram of our System...4 The DE2 Development and Educational Board..7 Nios II Processor Available Types..8 SOPC Builder.9 The FPGA Based Obstacle Avoidance Robot Platform.....9 Micro Servo Sg90..10 Control Signal for the Servo Motor...10 HC-SR04 Ultrasonic Sensor...10 Ultrasonic Sensor Working Principles..11 The L298 H-Bridge...11 The L298 H-Bridge Internal Circuitry..12 The Working Principle of the H-bridge....12 H-Bridge operations table..13 Computer and Design Software Tools.....13 Block Diagram of the Overall System... 14 Working Principle of the HC-SR04 Sonar Sensor 15 Servo Motor Signals and their Corresponding Positions..16 DC Motor Protective Circuit.....17 Hardware System Design.. 18 Screenshot of the SoPC Builder System..19 Nios II System Block....20 Trigger Generator Symbol File 20 Servo Motor PWM Generator Symbol File...21 DC Motor Direction Control Symbol File....21 DC Motor PWM Generator Symbol File...22 Top Level Schematic for the On-chip System....23 Compilation report.24 VIII

Figure 3.14 Figure 3.15 Figure 3.16 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Overall System RTL View 24 DC Motor Direction Control RTL View..25 The Overall System...25 Main Program Flow Chart 26 Scanning Procedure..27 Left and Right Obstacle Detection...28 Obstacle Avoidance Subroutine...30 A Path Following..31 Obstacle At the Starting Position..31 Robot At the Center of Three equally spaced obstacles 32 Segment of Nios II C code...33 IX

Chapter 1 Introduction

Chapter 1 Introduction 1.1. Overview Robotics is the branch of mechanical engineering, electrical engineering and computer science that deals with the design, construction, operation, and application of robots, as well as computer systems for their control, sensory feedback, and information processing. Throughout history, robotics has been often seen to mimic human behavior, and often manage tasks in a similar fashion. Today, robotics is a rapidly growing field, as technological advances continue; researching, designing, and building new robots serve various practical purposes, whether domestically, commercially, or militarily. Many robots do jobs that are hazardous to people such as defusing bombs, mines and exploring shipwrecks. Fully autonomous robots only appeared in the second half of the 20th century. The first digitally operated and programmable robot, the Unimate shown in Figure 1.1, was installed in 1961 to lift hot pieces of metal from a die casting machine and stack them. Commercial and industrial robots are widespread today and used to perform jobs more cheaply, or more accurately and reliably, than humans [1]. Figure 1.1 First Digitally Operated and Programmable Robot (Unimate) 1.2. Motivation Any mobile robot that must reliably operate in an unknown or dynamic environment must be able to perform obstacle avoidance. Therefore, there has been a great amount of research devoted to the obstacle avoidance problem for autonomous robot platforms and intelligent vehicles. Moreover, obstacle avoidance may be divided into two parts; obstacle detection and obstacle avoidance control. Page 1

Chapter 1 Introduction 1.3. Objective Our objective in this project is to design and implement a Field Programmable Gate Array (FPGA)-Based autonomous obstacle avoidance robot, using an ultrasonic sensor. First, the robot checks if no obstacle is ahead, and goes forward while nothing is in front of it. In the meanwhile, if any obstacle is detected, the motors stop. At this moment, the robot must decide which direction to turn to. In order to achieve that, the servo motor carrying the sensor rotates left and right, enabling the sensor to read the distance of all obstacles present in an angle of 180.Then, depending on the input signal from the sensor, the SoPC redirects the robot to move in an alternate direction by actuating the motors connected to it through a motor driver Integrated Circuit (IC). 1.4. Structure of the System Several platforms can be used to implement the digital controller of our system. Among them we can state the microprocessor, microcontroller, and FPGA. A microprocessor based system does not have the necessary circuitry on one chip, external devices are required such as memory, Input /Output buffers, in addition to a set of signals to transfer information, control signals for timing, and clock circuitry to constitute the overall architecture. Figure 1.2 shows an example a Z80 microprocessor based system. Figure 1.2 Microprocessor Based System. Page 2

Chapter 1 Introduction Since microprocessors do not have the necessary circuitry on one chip, another alternative, a microcontroller, can be used. A microcontroller is a small computer, with the advantage of gathering, on a single integrated circuit, all of the necessary components like a processor core, memory, programmable input/output peripherals and timers. However, microcontrollers already have their own circuitry and instruction set that the programmer must follow in order to write codes, which restricts the microcontroller to certain tasks. Figure 1.3 illustrates an example of a microcontroller including its components. Figure 1.3 Example of a Microcontroller Chip. The previous limitations led us to the FPGA, an integrated circuit that contains millions of logic gates, and can be electrically configured to perform a certain task. The very basic nature of FPGAs allows it to be more flexible than most microcontrollers. The term field programmable already tells that the whole FPGA device can be reprogrammed to do any logic task that fits the number of gates it has. Figure 1.4 shows an FPGA chip. Figure 1.4 Altera FPGA Chip. Page 3

Chapter 1 Introduction Due to the flexibility the FPGA offers, we chose to implement our digital controller by integrating a heterogeneous computing platform made up of microprocessor based system and some custom logic, all on a single chip. Our system consists of two main parts, Hardware and software. The software consists of the algorithms and the piece of code executed by the microprocessor to control the hardware part. This latter is detailed as following. FPGA Block contains the soft processor system as well as custom controlling units. Sensing unit consists of a single ultrasonic sensor that measures distances. Servo motor supports the sensing unit and rotates 180. Motor driver and DC Motors consists of an H-Bridge chip that receives control signals from the FPGA to actuate the DC motors direction. Interface block performs voltage translation between the FPGA and the Hardware components to make them compatible with each other. Servo Motor Sensing unit Motor Driver and DC Motors Interfacing Circuit SoPC FPGA Non-SoPC NIOS II Soft Processor I/O Peripherals Avalon Switch Interconnect Fabric Custom Logic Implemented with VHDL and LPM Units JTAG UART On-Chip Memory Figure 1.5 The general block diagram of the FPGA-based autonomous obstacle avoidance robot Page 4

Chapter 1 Introduction 1.5. Organization of the Report The report is organized into five chapters. Chapter 2 covers the theoretical background and introduces the different materials used in our project. Chapter 3 deals with the System hardware design. In chapter 4 the software design process and algorithm used to configure the FPGA are described. Chapter 5 concludes the report with recommendations for improvement and areas for further development. The report ends with a set of references for further readings. Page 5

Chapter 2 Theoretical Background

Chapter 2 Theoretical Background This chapter covers the theoretical background and the different components as well as their working principle. 2.1. Field-Programmable Gate Array (FPGA) A Field-Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together, like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory [1]. 2.1.1. Applications Technically, an FPGA can be used to solve any problem which is computable. This is trivially proven by the fact that FPGA can be used to implement a Soft microprocessor. Their advantage lies in that they are sometimes significantly faster for some applications due to their parallel nature and optimality in terms of the number of gates used for a certain process. Specific applications of FPGAs include digital signal processing, software-defined radio, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection and a growing range of other areas [1]. 2.1.2. The DE2 Development and Education Board The DE2 board shown in Figure 2.1 is an ideal platform for the implementation of many types of digital systems based on the FPGA introduced earlier. The board offers a rich set of features that make it suitable for a variety of design projects, as well as for the development of sophisticated digital systems. Page 6

Chapter 2 Theoretical Background Figure 2.1 The DE2 Development and Educational Board. 2.1.3. Soft core processors FPGAs can implement logic that functions as a complete microprocessor while providing many flexibility options. An important difference between discrete (hard) microprocessors and FPGAs is that an FPGA contains no logic when it powers up. Before you run software on a Nios II based system, the FPGA must be configured with a hardware design that contains a Nios II processor. To configure an FPGA is to electronically program the FPGA with a specific logic design [3]. Nios II processor Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. The Nios II architecture is a Reduced Instruction Set Computer ( RISC) soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals [1]. Nios II is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). The "standard" and "fast" variants are designed for high execution performance system. Figure 2.2 shows the options each variant offers. The use of the "fast" or the Page 7

Chapter 2 Theoretical Background "standard" version requires the purchase of an annual license from Altera. However, the "economy" variant is license free. Although limited, the Nios II/e running at 50MHz proofs to have a processing time that is large enough to be adequate for this control application [4]. Figure 2.2 Nios II Processor Available Types. 2.1.4 System on Programmable Chip SoPC SoPC (System on a Programmable Chip) is a hardware development tool used for integrating various hardware components. SoPC Builder simplifies the task of building complex hardware systems on an FPGA. It allows to describe the topology of a system using a graphical user interface (GUI) shown in Figure 2.3 and then generates the hardware description language (Verilog or VHDL) files for that system. In addition, it allows choosing the processor core type and the level of cache, debugging, and custom functionality for each Nios II processor. The design can use on-chip resources such as memory (RAM, ROM), memory controllers (SRAM, SDRAM), Serial interfaces (UART, SPI), Timers, PLLs, DSP functions, and high-speed transceivers. After constructing the system using SoPC Builder, and adding any required custom logic to complete the top-level design, pin assignments must be created using the Quartus II software. The FPGAs external pins have flexible functionality, and a range of pins is available to connect to clocks, control signals, and input /output - I/O signals [5]. Page 8

Chapter 2 Theoretical Background Figure 2.3 SoPC Builder. 2.2. The Robot The robot we are using in our project is a car with two 5V DC motors, one controls the forward and backward motions and the other is used for the direction. Figure2.4 The FPGA Based Obstacle Avoidance Robot Platform. Page 9

Chapter 2 Theoretical Background 2.3. Micro Servo Sg90 This section describes the Micro Servo Sg90 and the procedure to control its position. A servo motor is a motor that takes commands from a series of pulses with constant period of 20ms, and different duty cycles each corresponding to a specific position. The Micro servo Sg90, shown in Figure 2.5, works just like the standard kinds but is smaller, it can Figure 2.5 Micro Servo Sg90 rotate 180 degrees (90 in each direction). It can be seen from Figure 2.6 that the servo motor operates at approximately 5V. Here are some specific positions with their adequate signals: position "0" (1.5 ms pulse) is middle, "90" (~2 ms pulse) is all the way to the right, -90" (~1ms pulse) is all the way to the left [2]. Figure 2.6 Control signal for the servo motor. 2.4. Ultrasonic Sensor A sensor is a device that measures a physical quantity and converts it into a 'signal' which can be read by an observer or by an instrument. There are a lot of different types of sensors. In this part we introduce the HC-SR04 ultrasonic sensor, shown in Figure 2.7, and its working principle. Active ultrasonic sensors generate high frequency sound waves and evaluate the echo which is received back by the sensor, measuring the time interval between sending the signal and receiving the echo to determine the distance to an object as shown in Figure 2.8. Figure 2.7 HC-SR04 ultrasonic sensor. Page 10

Chapter 2 Theoretical Background Figure 2.8 Ultrasonic Sensor Working Principles. HC-SR04 Ultrasonic Distance Sensor is able to measure distances from 2cm to 400cm with an accuracy of about 3mm. This module includes ultrasonic transmitter, ultrasonic receiver and its control circuit, in addition to 4 pins. VCC 5V, positive of the power supply Trigger Trigger Pin ECHO Echo Pin GND negative of the power supply Trigger and ECHO pins are used to interface this module with the DE2 Board. Besides the wide range of measurable distances, this module has the advantage of returning digital data rather than analog, allowing us to avoid extending our circuitry by eliminating the Analog to Digital Conversion (ADC) unit. This is why we chose this ultrasonic sensor in our project. 2.5. H- Bridge In this part we are going to describe the H Bridge and its operations. An H bridge is an electronic circuit that enables a voltage to be applied across a DC motor in either direction (forward and backward).it is available as integrated circuits (L298), or can be built from discrete components Figure 2.9 The L298 H-Bridge. (transistors). The L298 shown in Figure2.9 has two H- Bridges inside, so that we can drive two DC motors simultaneously [1]. Page 11

Chapter 2 Theoretical Background Figure 2.10 illustrates the internal circuitry of the L298 H-bridge. We can see that 3 pins are devoted for the control of each motor; two are used for the direction control and the third is used for enabling the H-Bridge. Figure 2.10 The L298 H-Bridge Internal Circuitry [6]. The term H -Bridge is derived from the typical graphical representation of such a circuit. An H bridge is built with four switches (solid-state). When the switches S1 and S4 (according to Figure 2.11) are closed (and S2 and S3 are open) a positive voltage will be applied across the motor. By opening S1 and S4 switches and closing S2 and S3 switches, this voltage is reversed, allowing reverse operation of the motor. The switches S1 and S2 should never be closed at the same time, as this would cause a short circuit on the input voltage source. The same applies to the switches S3 and S4. This condition is known as shoot-through. Figure 2.11 The Working Principle of the H-bridge. Page 12

Chapter 2 Theoretical Background The following table summarizes the H- bridge operations, with S1-S4 corresponding to the above figure. S1 S3 S2 S4 Quadrant Description ON OFF OFF ON Forward Running OFF ON ON OFF Backward Running ON ON OFF OFF Braking OFF OFF ON ON Braking Figure 2.12 H-Bridge operations table. 2.6. Computer and Design Software Tools Figure 2.13 illustrates the hardware and software tools used in our system design. Quartus II, SoPC Builder and Nios II Integrated Development Environment (IDE). Quartus II enables to design any logic circuit and enables the developers to compile their designs, perform timing analysis, examine Register Transfer Level -RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus II software features include the SoPC Builder which has been used to create our microprocessor based system. This microprocessor is programmed using the Nios II IDE. Figure 2.13 Hardware and Software Tools. At this point, we illustrated the different components used for the obstacle avoidance implementation separately. What comes next, deals with the connection of these devices all together. Page 13

Chapter 3 Hardware System Design

Chapter 3 Hardware System Design 3.1. Introduction In this chapter we will detail the hardware system design of the autonomous obstacle avoidance robot. The system is made up of two main parts as illustrated in Figure 3.1. OFF chip system consists of the circuitry built on the proto-board. It connects the sensor, motor driving unit, servo motor, and bidirectional voltage translation unit. ON chip system implemented inside the FPGA. It gathers both SoPC and Non-SoPC systems; the SoPC system is composed of the Nios II Soft Processor, memory, JTAG and I/O ports. In the other hand, the Non-SoPC system contains some logic units developed in VHDL or LPMs, each dedicated for a specific function. OFF CHIP HARDWARE SYSTEM Sonar sensor Servo motor Bidirectional voltage level translation Motor driving unit DC motors ON CHIP HARDWARE SYSTEM NIOS II Processor SoPC System JTAG Non- SoPC System PWM generator for DC motors On chip memory Avalon switch fabric PIO Direction control block for DC motors PWM generator for servo motor Trigger signals for the sensor Figure 3.1 Block Diagram of the Overall System. Page 14

3.2. Off Chip Hardware Design Chapter 3 Hardware System Design This section deals with the Hardware circuit on the proto-board. This circuit is mainly composed of the following. o The Sensing unit and its support recover information about the environment by reading obstacle distances from different angles. o Motor driving unit interfaces the DC motors with the FPGA. o Bidirectional voltage translation unit ensures the interface between the FPGA and the off-chip circuitry implemented on the proto-board, by making the signals exchanged between them compatible with e ach other. 3.2.1. Sensing Unit and its Support Ultrasonic Sensor A single ultrasonic sensor of type HC-SR04 is used to detect the presence of any object in the robot environment. This module includes an ultrasonic transmitter, ultrasonic receiver and its control circuit. It is connected to the FPGA through two pins, ECHO pin and Trigger pin. The following figure shows the exchanged signals between the sensor and the DE2 board. Figure 3.2 Working Principle of the HC-SR04 Sonar Sensor. It can be seen from the Figure 3.2 that 2 signals are interchanged by the DE2 and the ultrasonic sensor. The first signal is a 10µS pulse, sent from the FPGA to the trigger pin of the sensor. This signal provokes the transmission of the eight 40 KHz ultrasonic burst. Page 15

Chapter 3 Hardware System Design Then, if there is an obstacle in-front of the module, it will reflect the ultrasonic burst as shown in Figure 2.8. This reflection is represented by a signal at the ECHO output of the sensor. This signal will be in HIGH state (5V) for the duration of time taken for sending and receiving the ultrasonic burst. Based on that duration and the speed of sound, we can calculate the distance of the obstacle reflecting the burst. The calculation, at a fixed position of the sensor, is done as following: If we let d to be the distance between the ultrasonic sensor and an obstacle, the Sensor will send a 2d digital signal to the ECHO port of the FPGA (the total distance traveled by the burst forward and backward). Also, since the speed of sound in the air is known to be 340 m/s = 34,000 cm/s, Thus d = (34,000*Time)/2. Since the dead time of data processing is very small we neglect it. To extend the area of study and detect the maximum number of obstacles present around the robot, we have to repeat the previous procedure from different angles. To achieve that, we fix the ultrasonic sensor on a servo motor. Servo Motor As mentioned earlier, a rotation of the ultrasonic sensor is required. To achieve that, we use the SG90 micro servo motor. This module is connected to the FPGA through a single pin and receives three successive signals from the FPGA. A PWM generator generates these three desired signals, to direct and fix the sensor at three specific positions as shown in the Figure 3.3. Figure 3.3 Servo Motor Signals and their Corresponding Positions. Page 16

3.2.2. Motor Driving Unit Chapter 3 Hardware System Design After the examination of the hardware design of the unit responsible of getting data related to the environment of the robot, we move to the hardware system used to interface the DC motors with the FPGA. H-Bridge The two DC motors of the robot respond to the data obtained from the ultrasonic sensor by changing the direction of rotation. To control the operation of each motor, three pins of the L298 H-Bridge are connected to the FPGA; two of these pins control the direction of rotation and the third one enables the bridge. However, this whole circuitry should be protected from certain damages. This is why we add a protective circuit. Protective Circuit To eliminate the undesirable inductive current from the DC motors and protect them from negative voltages, we build a protective circuit composed of diodes. Figure 3.4 shows the interfacing circuit of the DC motors with their protective circuitry. Figure 3.4 DC Motor Protective Circuit. Page 17

Chapter 3 Hardware System Design 3.2.3. Bidirectional Voltage Translation All the components covered in the Off chip hardware system operates under a voltage of approximately 5V. However, the DE2 board supplies only 3.3V. Consequently, we integrated a bidirectional voltage translation unit as a bridge between the previous components and the DE2 board. Figure 3.5 shows the entire hardware system design of our project. Figure 3.5 Hardware System Design. In this section, we dealt with the hardware design. The next one will be devoted to the solution of the On-chip system controlling the overall circuitry. 2.3. On Chip System Design This section treats the On-chip system managing the previous hardware circuit by defining relationships between the input and output signals. This system is implemented on the FPGA and is partitioned into SoPC and Non-SoPC modules. 2.3.1. SoPC System The SoPC system is based on the Nios II soft processor connected to the following functional units using the SoPC builder. Page 18

Chapter 3 Hardware System Design o Nios II/e processor executes the software system and generates the control signals. It operates under 50MHz. o On-chip memory consists on the memory blocks in the Cyclone II chip. We specified a 40Kbyte memory arranged in 32-bit words. o I/O Peripherals control the Non-SoPC modules (will be discussed in section 3.3.2) and the whole Off-chip system, we created the following I/O peripherals. Trigger 2-bits output signal that resets and enables the VHDL unit responsible of triggering the ultrasonic sensor. Echo 1-bit input signal that receives the digital data back from the sensor. Servo_Motor 4-bits output signal used to select the duty cycle of the signal generated by the PWM unit and sent to the servo motor. Motor_Displacement 2-bits output signal that activates the VHDL unit controlling the direction of the DC motor forward and backward. Motor_Direction 2-bits output signal that activates the VHDL unit controlling the direction of the DC motor left and right. o JTAG_UART peripheral: a component that provides a suitable way to link the host computer to communicate with the Nios II soft-core processor. Besides, a switch is used to reset the Nios II processor, and the JP1 expansion header connects the DE2 board to the external hardware circuit. Figure 3.6 shows the SoPC builder with the entire SoPC system. While Figure 3.7 shows the Nios II system block. Figure 3.6 Screenshot of the SoPC Builder System. Page 19

Chapter 3 Hardware System Design Figure 3.7 Nios II System Block. 3.3.2. Non-SoPC System We designed four different Non-SoPC units either using VHDL or LPMs. These units are controlled by the SoPC system, and consist of PWM for DC and servo motors, sensor trigger signal generator and DC motor direction control. Sensor Trigger Signal Generator As mentioned in section 3.2.1, the SR-HC04 sonar sensor requires a trigger pulse of at least 10µS in order to start transmitting the ultrasonic burst. To achieve this, we implemented a VHDL code in Quartus II, ensuring the generation of the required signal. Figure 3.8 shows the symbol file for this code. Figure 3.8 Trigger Generator Symbol File. Page 20

Servo Motor PWM Generator Chapter 3 Hardware System Design Toward setting the servo motor carrying the sensor to three specific positions, we implemented a PWM unit responsible for generating the three different signals seen previously in Figure 3.3. This system is implemented by a 32 to 1 multiplexer. The latter is driven by a 5-bit binary counter to ensure the required duty cycle, in addition to a 14-bit binary counter, used as a clock divider to generate a 20ms periodic signal. Figure 3.9 shows the symbol file for the PWM generator. Figure 3.9 Servo Motor PWM Generator Symbol File. DC Motor Direction Control Unit Once the SoPC processes the data to and from the preceding input modules, it actuates the direction of the DC motors through a specific unit shown in Figure 3.10. This unit is implemented on Quartus II in VHDL and is responsible for providing signals to the direction control pins of the H-Bridge. However, the H-bridge requires not only direction signals, but also an enable signal which will be discussed in the next section. Figure 3.10 DC Motor Direction Control Symbol File. Page 21

DC Motor PWM Generator Chapter 3 Hardware System Design As mentioned in section 3.2.2, the H-bridge has three pins for every motor. Two pins are used for direction control, and the third stands for enable. To control the speed of rotation, this enable is connected to a PWM generator. In our case, the PWM generator is implemented using a 32 to 1 LPM multiplexer driven by a 5-bit binary counter connected to the select lines of the multiplexer. The more successive ones we apply to the input of the latter, the higher the duty cycle will be. Figure 3.11 shows the symbol file of the PWM generator. Figure 3.11 DC Motor PWM Generator Symbol File. After covering both the SOPC and Non-SoPC systems, and creating a symbol file for all of the previous modules, it is time to link them all together with the Nios II soft processor in a single block diagram file. The resulting system is illustrated in Figure 3.12. The compilation of the whole system was successful. While examining the compilation report shown in Figure 3.13 we can see, in addition to the project characteristics that the entire system uses only 5% of the total logic elements, 3% of the total pins, 70% of the total memory bit, and 824 registers. We could also have access to the RTL viewer which allows us to view a schematic of the internal structure of the design. Furthermore, we could explore a high-level representation of our designed circuit, from which lower-level representations and ultimately actual wiring can be derived. Figure 3.14 shows the RTL view of the overall system. We selected the DC motor control block, as an example, and obtained its internal structure shown on Figure 3.15. Page 22

Figure 3.12 Top Level Schematic for the On-chip System. Chapter 3 Hardware System Design Page 23

Chapter 3 Hardware System Design Figure 3.13 Compilation Report. Figure 3.14 Overall System RTL View. Page 24

Chapter 3 Hardware System Design Figure 3.15 DC Motor Direction Control RTL View. Finally, the overall system is shown in Figure 3.16 including both the On-chip and Off-chip systems. Figure 3.16 The Overall System. At this stage, we finished with the hardware system design. What remains is the software system that will be presented in the next chapter. Page 25

Chapter 4 Software System Design

Chapter 4 Software System Design 4.1. Introduction Any embedded system is made of two parts: the hardware and software. Each of which is useless without the presence of the other. The software part is the one responsible of calculations, data manipulations and decision making. In this chapter we will deal with the programs and algorithms that constitute the software system of the autonomous obstacle avoidance robot. This software is written in C programming language and executed by the Nios II processor. 4.2. Main Program The main program is a program that links a set of subroutines. The flowchart of the main program is illustrated in Figure 4.1. Figure 4.1 Main Program Flow Chart. Page 26

Chapter 4 Software System Design The program starts by orienting the servo motor straight forward (position 0), and triggers the sensor in order to read the distance of the nearest forward obstacle D_Forward. In case the distance read is greater than a predefined distance D (60 cm), the robot continues moving forward and scans for any obstacle at the same time. However, if at any time the distance read is less than D, the robot stops moving and two subroutines are called successively. These subroutines are the obstacle detection left and right, and obstacle avoidance respectively. Once executed, the robot adjusts itself straight and resumes moving forward while repeating all previous procedures. The scanning procedure, obstacle detection and obstacle avoidance subroutines present in Figure 4.1 will be discussed in detail in the following sections. 4.3. Scanning Procedure The aim of this procedure is to compute the duration for the echo port to be high since this indicates the presence of an obstacle. It can be seen from Figure 4.2 that the procedure starts by triggering the sensor with the appropriate signal, and waits for Echo port to be high. While this port is high (1) a counter is incremented. Once the Echo port turns low (0) the final count is translated into distance according to the calculations shown in section 3.2.1. Figure 4.2 Scanning Procedure. Page 27

Chapter 4 Software System Design 4.4. Obstacle Detection As mentioned in the main program, obstacle detection left and right is required in case the robot cannot continue moving forward. Figure 4.3 shows its flowchart. Figure 4.3 Left and Right Obstacle Detection. Page 28

Chapter 4 Software System Design As stated in the main program description, the obstacle detection subroutine is called in case the sensor reads a forward obstacle distance smaller than the predefined distance D. Once called, an instruction is executed to fix the servo motor in the right direction (90 right with respect to its center). Then, the scan for obstacle subroutine is called to return the distance of the nearest obstacle on the right side of the robot D_Right. After that, another instruction is executed to direct the servo motor left (90 left with respect to its center) and the scan for obstacle subroutine is called again to get the D_Left. At this time, the three distances D_forward, D_Right and D_Left are known, we have to compare them to get the largest value L. 4.5. Obstacle Avoidance According to the main program flowchart in Figure 4.1, obstacle avoidance is executed once the obstacle detection procedure returns the largest distance L. This distance L refers to the suitable direction to turn to. Figure 4.4 describes the steps necessary to achieve this task. As it appears in Figure 4.4, the program verifies weather the forward distance is less than a predefined distance D1, the purpose of this verification is to check if the robot has enough space to turn left or right without colliding with the obstacle in front of it. If it is not the case, the robot moves backward in the direction of the nearest obstacle. Otherwise, if the largest distance matches the one on the right, the robot turns right and the flow of execution goes back to the main program. Else it will turn left. However, the largest distance whether it is on the right or the left must be greater than the predefined distance D1 (20 cm), to ensure that the robot does not stuck within the surrounding obstacles. A special case would be the one where left and right distances are equal and both less than D1, in this case the robot goes backward while scanning on both sides until it finds a suitable direction to turn to. An illustration of this case is shown in example 3 of section 4.6. Page 29

Chapter 4 Software System Design Figure 4.4: Obstacle Avoidance Subroutine. 4.6. Examples In this part we have chosen three examples to illustrate the behavior of the robot and to explain more our software. In those cases the robot has to avoid the obstacles in its way autonomously without any guidance. Figure 4.5 illustrates example 1 where the robot starts scanning forward and reads a distance greater than D. It starts, as a result moving forward and carry on while scanning. At position 3, the robot reads a forward distance less than D, which makes it stop. The servo motor carrying the sensor turns left and right and reads D_Left and D_right. At this point, the system performs a comparison of these distances and returns D_Right as the largest one. Page 30

Chapter 4 Software System Design Therefore, the robot turns right since both D_Forward and D_Right are large enough to allow it do that without colliding. P1 P2 P3 P4 P4 P: Position Motion direction of the robot. Scanning task. Figure 4.5 A Path Following. Figure 4.6 illustrates example 2 where the robot starts scanning forward and reads a distance less than D. As a result it scans left and right and finds that D_Right is the largest distance. However, D_Forward is not large enough to allow the robot turn. To gain more space to achieve that, the robot goes backward left and adjusts the wheels straight to move forward until it encounters another obstacle where it repeats the same steps. P1 P4 P3 P2 Figure 4.6 Obstacle At the Starting Position. Page 31

Chapter 4 Software System Design Figure 4.7 illustrates example 3 where the robot starts scanning forward and reads a distance less than D1. As a result it scans left and right and finds that the D_left and D_right are equal and both smaller than D1. In this case the robot cannot turn to any direction. Hence, it goes backward slowly and checks at the same time for the largest distance to turn to in this case it is the left direction. P1 P2 P2 P4 P3 Figure 4.7 Robot At the Center of Three equally spaced obstacles. 4.6. Programming Language The previous algorithms are programmed on the Nios II processor using C programming language. We chose C because it allows producing codes faster and more efficiently especially when dealing with print functions. In addition to the fact that it is a universally Page 32

Chapter 4 Software System Design available language; the code is easier to transport to different processors for further developments. The tool used to program these algorithms is the Nios II 9.1 Integrated Development Environment (IDE). Figure 4.8 illustrates a segment of the obstacle avoidance code in C. Figure 4.8 Segment of Nios II C Code. In these last two chapters, we covered both the hardware and software system designs of the FPGA-based obstacle avoidance robot. We will now establish a conclusion for the whole report with some suggestions for further improvements. Page 33

Chapter 5 Conclusion

Chapter 5 Conclusion Conclusion This report covered the design and the implementation of an FPGA-Based obstacle avoidance robot. The two main tasks of the controller are obstacle detection and obstacle avoidance. The use of the FPGA as the platform for developing the digital control system appeared to be of great advantage due to its high speed and configurability. SoPC technique was also used to implement the Nios II processor based system associated with other custom logic. The main advantages of this approach are: Flexibility in using the exact number of peripherals desired,the suitable memory size and the processor core type. The heterogeneous computer platform partitions tasks between the SoPC and Non- SoPC systems. This prevents the SoPC from performing all the tasks by itself. The rotating sonar system gives a more accurate position for the obstacle and provides us with the advantage of using only one sensor. Despite the low-cost Cyclone-II FPGA platform and the economic version of the Nios II used, all required resources are provided to meet successfully all the objectives set at the beginning of the project. However, further improvements to enhance the robot are stated below. A wireless technique, between the DE2 Board and the Hardware circuitry, would be more efficient to allow the robot move freely without being limited by the length of the wires. An additional sensor at the back of the robot would make the obstacle avoidance more efficient. Using a printed circuit board would reduce the size of the circuit on the proto-board. To have a better control of the system speed, encoders could be used for the DC motors. Page 34

References References [1] www.wikipedia.com [2] http://datasheet.sparkgo.com.br/sg90servo.pdf [3] www.altera.com. [4] Benzid Sofiane, Douba Mohammed Lamine, FPGA-Based Design Process of an Object Arrangement and Obstacle Avoidance Controller. Final Year Project Report in Electrical Engineering Option : Control. Institute of Electrical and Electronic Engineering, UMBB, June 2013. [5] http://sites.google.com/site/ahmedmaache/ [6] www.alldatasheet.com/datasheet-pdf/pdf/22437/stmicroelectronics/l298.html [7] SoPC Builder user Guide: http://www.altera.com/literature/ug/ug_sopc_builder.pdf. [8] www.datasheet.sparkgo.com.br/sg90servo.pdf. [9] Introduction to the Altera NIOS II soft processor user guide. [10] Introduction to the Altera SOPC Builder using VHDL Design user guide. [11] L298 H Bridge data sheet. [12] Sachin Modi, Comparison of Three Obstacle Avoidance Methods for an Autonomous Guided Vehicle. Master of Science Degree Thesis, Department of Mechanical, Industrial and Nuclear Engineering, College of Engineering, 2002. [13] http://www.electroschematics.com/8902/hc-sr04-datasheet/ [14] www.acroname.com/robotics/info/articles/sharp/sharp.html Page 35