PD -97364A IRLS334PbF IRLSL334PbF Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D S HEXFET Power MOSFET V DSS 4V R DS(on) typ. 1.4m: max. 1.7m: I D (Silicon Limited) 343Ac I D (Package Limited) 195A Benefits l Optimized for Logic Level Drive l Very Low R DS(ON) at 4.5V V GS l Superior R*Q at 4.5V V GS l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l Lead-Free D S G D 2 Pak IRLS334PbF D S D G TO-262 IRLSL334PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 343c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 243 c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 195 A I DM Pulsed Drain Current d 1372 P D @T C = 25 C Maximum Power Dissipation 375 W Linear Derating Factor 2.5 W/ C V GS Gate-to-Source Voltage ±2 V dv/dt Peak Diode Recovery f 4.6 V/ns T J Operating Junction and T STG Storage Temperature Range -55 to 175 Soldering Temperature, for seconds (1.6mm from case) 3 C Mounting torque, 6-32 or M3 screw lbfxin (1.1Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 255 mj I AR Avalanche Current d A See Fig. 14, 15, 22a, 22b, E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc Junction-to-Case kl.4 R θja Junction-to-Ambient (PCB Mount) j 4 C/W www.irf.com 1 7/2/9
IRLS/SL334PbF Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 4 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.4 V/ C Reference to 25 C, I D = 5mAd R DS(on) Static Drain-to-Source On-Resistance 1.4 1.7 V GS = V, I D = 195A g mω 1.6 2. V GS = 4.5V, I D = 172A g V GS(th) Gate Threshold Voltage 1. 2.5 V I DSS I GSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage 2 Gate-to-Source Reverse Leakage 25 - µa na R G(int) Internal Gate Resistance 2.1 Ω Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 286 S V DS = V, I D = 195A Q g Total Gate Charge 8 162 I D = 185A Q gs Gate-to-Source Charge 29 Q gd Gate-to-Drain ("Miller") Charge 54 Q sync Total Gate Charge Sync. (Q g - Q gd ) 54 t d(on) Turn-On Delay Time 65 t r Rise Time 827 t d(off) Turn-Off Delay Time 97 t f Fall Time 355 C iss Input Capacitance 315 C oss Output Capacitance 198 C rss Reverse Transfer Capacitance 935 C oss eff. (ER) Effective Output Capacitance (Energy Related)i 2378 C oss eff. (TR) Effective Output Capacitance (Time Related) h 2986 Diode Characteristics Symbol Parameter Min. Typ. Max. Units V DS = V GS, I D = 25µA V DS = 4V, V GS = V V DS = 4V, V GS = V, T J = 125 C V GS = 2V V GS = -2V V DS = 2V V GS = 4.5V g I D = 185A, V DS =V, V GS = 4.5V V DD = 26V I D = 195A R G = 2.1Ω V GS = 4.5V g V GS = V V DS = 25V ƒ = 1.MHz V GS = V, V DS = V to 32V i V GS = V, V DS = V to 32V h Conditions I S Continuous Source Current MOSFET symbol 343c (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 1372 (Body Diode)d p-n junction diode. V SD Diode Forward Voltage 1.3 V, I S = 195A, V GS = V g t rr Reverse Recovery Time 39 V R = 34V, ns 41 T J = 125 C I F = 195A Q rr Reverse Recovery Charge 39 di/dt = A/µs g 46 nc T J = 125 C I RRM Reverse Recovery Current 1.7 A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) nc ns pf D S Notes: Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 195A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L =.13mH R G = 25Ω, I AS = 195A, V GS =V. Part not recommended for use above this value. I SD 195A, di/dt 841A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to applocation note # AN-994. R θ is measured at T J approximately 9 C Š R θjc value shown is at time zero 2 www.irf.com
C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLS/SL334PbF VGS TOP 15V V 8.V 4.5V 3.5V 3.V 2.7V BOTTOM 2.5V 6µs PULSE WIDTH Tj = 25 C VGS TOP 15V V 8.V 4.5V 3.5V 3.V 2.7V BOTTOM 2.5V 6µs PULSE WIDTH Tj = 175 C 2.5V 2.5V 1.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics.1 1 V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics 2. I D = 195A V GS = V T J = 175 C 1.5 1. 1 V DS = 25V 6µs PULSE WIDTH.1 1 2 3 4 5 V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics.5-6 -4-2 2 4 6 8 12141618 T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature V GS = V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 5. 4.5 4. I D = 185A V DS = 32V V DS = 2V C iss C oss 3.5 3. 2.5 C rss 2. 1.5 1.. 1 2 4 6 8 12 14 V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3.5
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) IRLS/SL334PbF T J = 175 C V GS = V 1...5 1. 1.5 2. 2.5 V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 35 3 25 2 Limited By Package 1 5 48 46 V DS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area Id = 5mA OPERATION IN THIS AREA LIMITED BY R DS (on) LIMITED BY PACKAGE Tc = 25 C Tj = 175 C Single Pulse µsec 1msec msec.1.1 1 DC 15 44 5 42 2.5 2. 1.5 1..5 25 5 75 125 15 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 4-6 -4-2 2 4 6 8 12141618 T J, Temperature ( C ) 12 8 6 4 2 Fig. Drain-to-Source Breakdown Voltage I D TOP 38.9A 65.3A BOTTOM 195A. 5 15 2 25 3 35 4 45 25 5 75 125 15 175 V DS, Drain-to-Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 11. Typical C OSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRLS/SL334PbF 1 Thermal Response ( Z thjc ) C/W.1.1 D =.5.2..5.2.1 SINGLE PULSE ( THERMAL RESPONSE ) R 1 R 1 R 2 R 2 R 3 R 3 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri R 4 Ri ( C/W) τi (sec) R 4.2477.25.481.848 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc.1 1E-6 1E-5.1.1.1.1 t 1, Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case τ 4 τ 4 τ C τ.84.77.1957.1656 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 15 C and Tstart =25 C (Single Pulse).1.5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 15 C. 1 1.E-6 1.E-5 1.E-4 1.E-3 1.E-2 1.E-1 tav (sec) 3 25 2 15 5 TOP Single Pulse BOTTOM 1.% Duty Cycle I D = 195A 25 5 75 125 15 175 Starting T J, Junction Temperature ( C) Fig 15. Maximum Avalanche Energy vs. Temperature Fig 14. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 14, 15: (For further info, see AN-5 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 13) P D (ave) = 1/2 ( 1.3 BV I av ) = DT/ Z thjc I av = 2DT/ [1.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR (A) I RRM (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RRM (A) IRLS/SL334PbF 3. 2.5 2. 14 12 I F = 78A V R = 34V T J = 125 C 1.5 8 1..5 I D = 25µA I D = 1.mA ID = 1.A 6 4 2. -75-5 -25 25 5 75 125 15 175 T J, Temperature ( C ) Fig 16. Threshold Voltage vs. Temperature 2 3 4 5 di F /dt (A/µs) Fig. 17 - Typical Recovery Current vs. di f /dt 14 12 I F = 117A V R = 34V 4 I F = 78A V R = 34V T J = 125 C 3 T J = 125 C 8 6 2 4 2 2 3 4 5 2 3 4 5 di F /dt (A/µs) Fig. 18 - Typical Recovery Current vs. di f /dt di F /dt (A/µs) Fig. 19 - Typical Stored Charge vs. di f /dt 4 3 I F = 117A V R = 34V T J = 125 C 2 2 3 4 5 di F /dt (A/µs) Fig. 2 - Typical Stored Charge vs. di f /dt 6 www.irf.com
IRLS/SL334PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs 15V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.1Ω - V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G - V DD VV GS Pulse Width 1 µs Duty Factor.1 % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 12V.2µF.3µF V GS D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7
IRLS/SL334PbF D 2 Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D 2 Pak (TO-263AB) Part Marking Information 7,6,6$1,5)6:,7 /27&2'(,17(51$7,21$/ $66(%/('21:: 5(&7,),(5,17($66(%/</,1(/ /2*2 $66(%/< /27&2'( )6 3$5718%(5 '$7(&2'( <($5 :((. /,1(/ 25,17(51$7,21$/ 5(&7,),(5 /2*2 $66(%/< /27&2'( )6 3$5718%(5 '$7(&2'( 3 '(6,*1$7(6/($')5(( 352'8&7237,21$/ <($5 :((. $ $66(%/<6,7(&2'( Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com
IRLS/SL334PbF TO-262 Package Outline Dimensions are shown in millimeters (inches) TO-262 Part Marking Information (;$3/( 7,6,6$1,5// /27&2'( $66(%/('21::,17($66(%/</,1(&,17(51$7,21$/ 5(&7,),(5 /2*2 $66(%/< /27&2'( 3$5718%(5 '$7(&2'( <($5 :((. /,1(& 25,17(51$7,21$/ 5(&7,),(5 /2*2 $66(%/< /27&2'( 3$5718%(5 '$7(&2'( 3 '(6,*1$7(6/($')5(( 352'8&7237,21$/ <($5 :((. $ $66(%/<6,7(&2'( Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRLS/SL334PbF D 2 Pak (TO-263AB) Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.6 (.63) 1.5 (.59) 4. (.161) 3.9 (.153) 1.6 (.63) 1.5 (.59).368 (.145).342 (.135) FEED DIRECTION TRL 1.85 (.73) 1.65 (.65) 11.6 (.457) 11.4 (.449) 15.42 (.69) 15.22 (.61) 24.3 (.957) 23.9 (.941).9 (.429).7 (.421) 16. (.634) 15.9 (.626) 1.75 (.69) 1.25 (.49) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.5 (.532) 12.8 (.54) 27.4 (1.79) 23.9 (.941) 4 33. (14.173) MAX. 6. (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.4 (1.39) 24.4 (.961) 3 3.4 (1.197) MAX. 4 Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 252-75 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information. 7/29 www.irf.com