Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25 1 October 2014 Fabr ication of FET circuits is a complex enter prise A circuit designer relates to the fabr ication process indirectly The device electrical character istics are determined by the fabr ication recipe the device models such SPICE or other simulation The device physical character istics are determined by the resolution of the lithography the design rules, extraction rules The circuit perfor mance combines electrical and physical character istics with design decisions Substrates in MOS doped n or p type Silicon (Chemical Symbol Si) NFET is assembled in, on and over p-type Si PFET is assembled in, on and over n-type Si 2 October 2014
CMOS requires both NFET and PFET devices hence n- type Si and p-type Si is needed Well is a region of the opposite type as the substrate Example: A n-type substrate (doped with phosphorus (P)) is compensation doped p-type (doped with boron (B)) Yields a p-type region on the n-type substrate for the constr uction of one or (typically) more NFETs Process flow steps Processing steps for 0. 18µm range from 200-400 The FET requires 6-10 layers and each layer ofmetal interconnect 2 or 3 additional layers Metal interconnect layers range from four to seven Most steps require well-controlled chemistry, optics, and mechanical handling. 3 October 2014 Substrate doping concentrations are less than 10 15 atoms/cm 3 Wafer back-grinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like asmar t- card or PCMCIA card.) Processing steps http://en.wikipedia.org/wiki/ Semiconductor_device_fabrication#List_of_steps in modern electronic device manufacture (not necessarily a specific order) include wafer processing, die processing, package processing, and testing Wafer processing Wet cleans Photolithography Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased) conductivity) 4 October 2014
Dr y etching Wet etching Plasma ashing Ther mal treatments Rapid thermal anneal Fur nace anneals Ther mal oxidation Chemical vapor deposition (CVD) Physical vapor deposition (PVD) Molecular beam epitaxy (MBE) Electro-chemical Deposition (ECD). See Electro-plating Chemical-mechanical planarization (CMP) 5 October 2014 Wafer testing (where the electrical perfor mance is ver ified) Die preparation Wafer mounting Die cutting IC packaging Die attachment IC Bonding Wire bonding Flip chip Tab bonding IC encapsulation Baking 6 October 2014
Plating Laser-mar king Trim and for m IC testing Patter ning transfer image from mask to current surface of semiconductor wafer Typically photolithography Light sensitive mater ial called photoresist changes chemically after exposure to light Patter n is obtained by removing exposed areas (positive) or unexposed areas (negative) Create n-well regions What is the substrate in this case? Grow oxide SiO2 silicon dioxide is the heart and soul of Si MOSFET technology 7 October 2014 Field Oxide isolates wires and conductors Field-Ox approximately 1000 angstroms thick Gate Oxide isolate controlling terminal (gate) from conducting channel Gate-Ox is approximately 10 angstroms thick Deposit and Patter n polysilicon polysilicon replaced the or iginal metal (Al) for the gate An amorphous crystal can be patterned more precisely than a metal Doped to yield a conductor with low resistivity Polysilicon patterning is so-called self-aligned Implant transistor terminals, substrate and well contacts each source or drain terminal for ms a reversed biased pn diode 8 October 2014
Open contact holes (windows) and deposit and pattern metal signal conductors are an alloy ofmostly Al and Cu and, more recently Cu Each technology generation requires special structures Polysilicon Self-aligned gate - introduced long ago Grow gate oxide with the sum of the both N active, P active and gate masks Deposit polysilicon (gate electrode) Patter n all polysilicon Etch (remove) gate oxide not patterned by polysilicon (active mask) Implant each active area separately 9 October 2014 Silicide for mation to lower the intrinsic resistance of polysilicon Local interconnects for m a ohmic connection between active and polysilicon without a metal contact Drain engineering Goal is to improve character istics of MOS transistors with ultra-shor t channel. Lightly-doped drain - limit oxide damage from hot electron effects Drain engineering - modifications of the drain and channel region adjacent to drain Lower concentrations (10 18 20 ) Shallow and near the gate-oxide boundary 10 October 2014
Cross section of FET. Note the active doping var iation is several orders of magnitude lower near channel 11 October 2014 Acompleted wafer is finally passivated (a glass covering) Contact holes through passivation allow for contact to the package and the outside wor ld Testing is on-going during processing steps, at the waferlevel, package and in the field. Pr inting the pattern of the physical layout is imperfect Defects on the raw, original wafer interfere with printing Each mask has to have precise focus to transfer the patter n to the wafer Mask is the size ofasingle die to as many asdozen die but never entire wafer Focus at wafer edge less reliable than the center Resists and material removed can leave unwanted par ticles on wafer 12 October 2014
Implant, deposition and other addition steps can leave trace materials After each major step (polysilicon, metal1, metal2...) the wafer isreplanar ized 13 October 2014 Photo from IBM 14 October 2014
Cross section MOSFET, Photo from LSI Logic 15 October 2014 Pinhole in MOSFET gate oxide, Photo from LSI Logic 16 October 2014
Metal bridge, Photo from LSI Logic 17 October 2014 No channel junction in MOSFET, Photo from LSI Logic 18 October 2014
Physical design defines the patterns to be transferred during fabr ication Physical design is largely controlled by CAD tools Each transistor, the interconnect wires linking them, the power distr ibution, input and output pads are all specified on a 2-dimensional grid ofcoordinates Layout Design Rules are also known as Physical Design Rules and as just Design Rules Layout Design Rules the contract between the intended circuit and fabr ication Any semiconductor technology CMOS, Bipolar etc. have design rules Each technology node such as 0. 25µm versus 0. 18µm will have different design rules 19 October 2014 Design Rules evolve asthe processing for a technology matures Physical Design Rules are the result of what can be physically patterned on the wafer and electrical considerations such field strength, capacitive coupling and the like In some cases two sets of design rules are specified; one set for physical limitations of the fabr ication and a second set detailing the electrical limitations Design rules for both physical and electrical properties specified in physical dimensions Scaling a technologies physical dimensions by a constant factor is one path from technology node to technology node In this situation it is common to define design rules on a dimensionless grid called the lambda grid (λ) 20 October 2014
Constant scaling of physical design rules wor ks well at larger dimensions (ie 0. 8µm and above) At smaller dimensions a single scaling factor the physical design rules may be ver y conser vative potential significant perfor mance loss 21 October 2014 Circuit Topo Est. Parasitics Size FETs Prelim Layout Mask Layout DRC Extraction Simulation Optimization Specifications Design flow at right combines physical and circuit design layers Physical design limited by the geometric design rules Circuit design uses simulation models of active and passive devices Optimization for circuit design includes; power, area, delay, input/output load Optimization may force changes at topology entr y point 22 October 2014
Polysilicon Length Active Extension Contact Cut 111111 000000 000000 111111 111111 000000 Separation Width Active Active Active Design rule types Polysilicon Extension Width minimum pattern feature of active layer Length minimum pattern feature of a polysilicon gate (ie transistor) 23 October 2014 Separation minimum distance between two electr ically different nodes on same layer minimum distance between two different layers Extension and Overhang minimum distance that one layer must cover another Ever y layer such as metal 1, metal 2,... metal N, polysilicon, contacts, vias etc. has design rules for inter-layer physical restr ictions and intra-layer restr ictions MOSIS design rules used in class are simplified Scalable λ rules 1111111 0000000 11111 00000 00000 11111 11111 00000 Conser vative to limit the number of conditions to consider Complete description located at http://www.mosis.edu/technical/designr ules/scmos/ 24 October 2014
Mosis design rules for metal 1 Rule Description λ 7.1 Minimum width 3 7.2 Minimum spacing 2 7.3 Minimum overlap of any contact 1 7.4 Minimum spacing when either metal line is wider than 10λ 4 25 October 2014 Mosis design rules for p-type and n-type active Rule Description λ 2.1 Minimum width 3 2.2 Minimum spacing 3 2.3 Source/Drain active towell edge 5 2.4 Substrate/well contact active towell edge 3 2.5 Minimum spacing between non-abutting active 4 26 October 2014
Mosis design rules for vias Rule Description λ 8.1 Exact size 2x2 8.2 Minimum via 1 spacing 3 8.3 Minimum overlap by metal1 1 8.4 Minimum spacing to contact 2 8.5 Minimum spacing to poly or active edge 2 27 October 2014 Design rules are derived for correct by constr uction Via rule 8.1 result in a reasonable guarantee (defects per tr illion) that every via will be manufactured correctly Metal and active rules 2.1 and 7.1 limit the minimum feature size ofamater ial Other design rules address reliability of final circuits Antenna rules limit process induced damage of gate oxides Polysilicon and metal collect charge during reactive ion etch Connected to gate oxide the collected charge develops potentials for significant tunneling current through the thin oxide Time Dependent Dielectric Breakdown (TDDB) reliability requirements limit wire length connected gate oxide 28 October 2014
Metal1 signal distribution structure then a "cut and link" method using shorter lengths of metal1 and metal2 Resoultion enhancement techniques Eventually resolution enhancement flows upstream into design space ADesigner s Guide to Subresolution Lithography: Enabling the Impossible to Get to the 14-nm Node http://ieeexplore.ieee.org/stamp/ stamp.jsp?tp=&arnumber=6491444 Area fill add dummy mater ial in spaces for each layer to for amore unifor m density Source light wavelengths longer than image feature size are poorly reproduced Control focus etc. insufficient to create sharp images Optical proximty correction modifies design mask shapes to shapes which sharpen image on wafer 29 October 2014 Off-axis imaging opens the angle of the light source to the wafer double pattern/exposure techniques separate one layer into several masks No process produces a perfect result All physical measurements of process layers are distributions Thickness of gate oxide, implants change VT Metal thickness, vias, contacts change wire resistances Typical distributions are Unifor m(), Nor mal() and Lognormal() The effect of the var iation is no two transistors source/sink the same current Compensate for the var iation by designing a var iation tolerance 30 October 2014
Design Margins simulate or test devices under multiple conditions to reveal design sensitivity Design corner on transistors (fast, nominal, slow) Chip voltages 1. 1VDD, VDD, 0.9VDD Chip (junction) temperature 0 o C,75 o C,125 o C, Variation tracking is an additional step to design to further reduce effect of processing Delay tracking uses dummy copies of timing critical paths Device matching with layout techniques such as using 2 parallel transistors instead of twice the width 31 October 2014