W/ C V GS Gate-to-Source Voltage ±20 dv/dt Peak Diode Recovery f 4.6. V/ns T J. mj I AR. Avalanche Current d A See Fig. 14, 15, 22a, 22b, E AR

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PD 97363 IRLB334PbF Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D S HEXFET Power MOSFET V DSS 4V R DS(on) typ..4m: max..7m: I D (Silicon Limited) 343Ac I D (Package Limited) 95A Benefits l Optimized for Logic Level Drive l Very Low R DS(ON) at 4.5V V GS l Superior R*Q at 4.5V V GS l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree TO22AB IRLB334PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 343c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 243 c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 95 A I DM Pulsed Drain Current d 372 P D @T C = 25 C Maximum Power Dissipation 375 W Linear Derating Factor 2.5 W/ C V GS GatetoSource Voltage ±2 V dv/dt Peak Diode Recovery f 4.6 V/ns T J Operating Junction and T STG Storage Temperature Range 55 to 75 Soldering Temperature, for seconds (.6mm from case) 3 C Mounting torque, 632 or M3 screw lbfxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 255 mj I AR Avalanche Current d A See Fig. 4, 5, 22a, 22b, E AR Repetitive Avalanche Energy d mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase j.4 R θcs CasetoSink, Flat, Greased Surface.5 R θja JunctiontoAmbient 62 C/W www.irf.com /4/9

IRLB334PbF Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 4 V V GS = V, I D = 25µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.4 V/ C Reference to 25 C, I D = 5mAd R DS(on) Static DraintoSource OnResistance.4.7 V GS = V, I D = 95A g mω.6 2. V GS = 4.5V, I D = 72A g V GS(th) Gate Threshold Voltage. 2.5 V I DSS I GSS DraintoSource Leakage Current GatetoSource Forward Leakage 2 GatetoSource Reverse Leakage 25 µa na R G(int) Internal Gate Resistance 2. Ω Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 286 S V DS = V, I D = 95A Q g Total Gate Charge 8 62 I D = 85A Q gs GatetoSource Charge 29 Q gd GatetoDrain ("Miller") Charge 54 Q sync Total Gate Charge Sync. (Q g Q gd ) 54 t d(on) TurnOn Delay Time 65 t r Rise Time 827 t d(off) TurnOff Delay Time 97 t f Fall Time 355 C iss Input Capacitance 35 C oss Output Capacitance 98 C rss Reverse Transfer Capacitance 935 C oss eff. (ER) Effective Output Capacitance (Energy Related)i 2378 C oss eff. (TR) Effective Output Capacitance (Time Related) h 2986 Diode Characteristics Symbol Parameter Min. Typ. Max. Units V DS = 2V V GS = 4.5V g I D = 85A, V DS =V, V GS = 4.5V V DD = 26V I D = 95A R G = 2.Ω V GS = 4.5V g V GS = V V DS = 25V ƒ =.MHz V GS = V, V DS = V to 32V i V GS = V, V DS = V to 32V h I S Continuous Source Current MOSFET symbol 343c (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 372 (Body Diode)d pn junction diode. V SD Diode Forward Voltage.3 V, I S = 95A, V GS = V g t rr Reverse Recovery Time 39 V R = 34V, ns 4 T J = 25 C I F = 95A Q rr Reverse Recovery Charge 39 di/dt = A/µs g 46 nc T J = 25 C I RRM Reverse Recovery Current.7 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) nc ns pf V DS = V GS, I D = 25µA V DS = 4V, V GS = V V DS = 4V, V GS = V, T J = 25 C V GS = 2V V GS = 2V Conditions D S Notes: Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 95A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L =.3mH R G = 25Ω, I AS = 95A, V GS =V. Part not recommended for use above this value. I SD 95A, di/dt 84A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. ˆ R θ is measured at T J approximately 9 C 2 www.irf.com

C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) IRLB334PbF VGS TOP 5V V 8.V 4.5V 3.5V 3.V 2.7V BOTTOM 2.5V 6µs PULSE WIDTH Tj = 25 C VGS TOP 5V V 8.V 4.5V 3.5V 3.V 2.7V BOTTOM 2.5V 6µs PULSE WIDTH Tj = 75 C 2.5V 2.5V. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics. V DS, DraintoSource Voltage (V) Fig 2. Typical Output Characteristics 2. I D = 95A V GS = V T J = 75 C.5. V DS = 25V 6µs PULSE WIDTH. 2 3 4 5 V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics.5 6 4 2 2 4 6 8 2468 T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 5. 4.5 4. I D = 85A V DS = 32V V DS = 2V C iss C oss 3.5 3. 2.5 C rss 2..5. V DS, DraintoSource Voltage (V) Fig 5. Typical Capacitance vs. DraintoSource Voltage. 2 4 6 8 2 4 Q G, Total Gate Charge (nc) Fig 6. Typical Gate Charge vs. GatetoSource Voltage www.irf.com 3.5

Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) DraintoSource Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) IRLB334PbF T J = 75 C V GS = V...5..5 2. 2.5 V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage 35 3 25 2 Limited By Package 5 48 46 V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating Area Id = 5mA OPERATION IN THIS AREA LIMITED BY R DS (on) LIMITED BY PACKAGE Tc = 25 C Tj = 75 C Single Pulse µsec msec msec.. DC 5 44 5 42 2.5 2..5..5 25 5 75 25 5 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 4 6 4 2 2 4 6 8 2468 T J, Temperature ( C ) 2 8 6 4 2 Fig. DraintoSource Breakdown Voltage I D TOP 38.9A 65.3A BOTTOM 95A. 5 5 2 25 3 35 4 45 25 5 75 25 5 75 V DS, DraintoSource Voltage (V) Starting T J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com

Avalanche Current (A) E AR, Avalanche Energy (mj) IRLB334PbF Thermal Response ( Z thjc ) C/W.. D =.5.2..5.2. SINGLE PULSE ( THERMAL RESPONSE ) R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i Ri R 4 Ri ( C/W) τi (sec) R 4.2477.25.48.848 Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc. E6 E5.... t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ 4 τ 4 τ C τ.84.77.957.656 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse)..5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 5 C..E6.E5.E4.E3.E2.E tav (sec) 3 25 2 5 5 TOP Single Pulse BOTTOM.% Duty Cycle I D = 95A 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5

Q RR (A) I RRM (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RRM (A) IRLB334PbF 3. 2.5 2. 4 2 I F = 78A V R = 34V T J = 25 C.5 8..5 I D = 25µA I D =.ma ID =.A 6 4 2. 75 5 25 25 5 75 25 5 75 T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 3 4 5 di F /dt (A/µs) Fig. 7 Typical Recovery Current vs. di f /dt 4 2 I F = 7A V R = 34V T J = 25 C 4 3 I F = 78A V R = 34V T J = 25 C 8 6 2 4 2 2 3 4 5 di F /dt (A/µs) Fig. 8 Typical Recovery Current vs. di f /dt 2 3 4 5 di F /dt (A/µs) Fig. 9 Typical Stored Charge vs. di f /dt 4 3 I F = 7A V R = 34V T J = 25 C 2 2 3 4 5 di F /dt (A/µs) Fig. 2 Typical Stored Charge vs. di f /dt 6 www.irf.com

IRLB334PbF D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G V DD VV GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 2V.2µF.3µF V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7

IRLB334PbF TO22AB Package Outline Dimensions are shown in millimeters (inches) TO22AB Part Marking Information (;$3/( 7,6,6$,5) /27&2'( $66(%/('2::,7($66(%/</,(& RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(%/< /27&2'( 3$578%(5 '$7(&2'( <($5 :((. /,(& TO22AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 25275 TAC Fax: (3) 252793 Visit us at www.irf.com for sales contact information. /9 8 www.irf.com