Interconnect Planning, Synthesis, and Layout for Performance, Signal Reliability and Cost Optimization. Project Overview

Ineconnec Planning, Synhesis, and Layou fo Pefomance, Signal Reliabiliy and Cos Opimizaion SRC Task ID: 605.00 PI: Pof. Jason Cong (UCLA) Gaduae Sudens: Chin-Chih Chang, Daid Pan, Xin Yuan Indusial Liaisons: D. Pakash Aunachalam (Inel) D. Noman Chang (HP) D. Wilm Donah (IBM) D. Sefan Rusu (Inel) SRC Monio: Lawence Aledge (SRC) Pojec Oeiew Objecie: inesigae an ineconnec-cenic design flow and mehodology, consising of: Ineconnec Planning Ineconnec Synhesis Ineconnec Layou

Oeiew of Ineconnec-Cenic IC Design Flow Achiecue/Concepual-leel Design Design Specificaion HDM Ineconnec Planning Physical Hieachy Geneaion Fooplan/Coase Placemen wih Ineconnec Planning Ineconnec Achiecue Planning Ineconnec Pefomance Esimaion Models (IPEM) OWS, SDWS, BISWS Sucue iew Funcional iew Physical iew Timing iew Synhesis and Placemen unde Physical Hieachy Ineconnec Synhesis Pefomance-dien Global Rouing Pseudo Pin Assignmen unde Noise Conol Ineconnec Layou Roue Planning Poin-o-Poin Gidless Rouing absacion Ineconnec Opimizaion (TRIO) Topology Opimizaion wih Buffe Inseion Wie sizing and spacing Simulaneous Buffe Inseion and Wie Sizing Simulaneous Topology Consucion wih Buffe Inseion and Wie Sizing Final Layou Oeiew of Ineconnec-Cenic IC Design Flow Achiecue/Concepual-leel Design HDM Sucue iew Funcional iew Physical iew Timing iew Design Specificaion Ineconnec Planning Ineconnec Pefomance Ineconnec Planning Physical Hieachy Geneaion Esimaion Ineconnec Models Pefomance (IPEM) Physical Hieachy Geneaion Esimaion Models (IPEM) Fooplan/Coase Placemen Placemen wih Ineconnec wih Planning OWS OWS, SDWS, BISWS Ineconnec Achiecue Planning SDWS Ineconnec Achiecue Planning BISWS Synhesis and Placemen unde Physical Hieachy absacion Ineconnec Synhesis Ineconnec Opimizaion (TRIO) Ineconnec Opimizaion Ineconnec Synhesis Pefomance-dien (TRIO) Pefomance-dien Global Global Topology Rouing Rouing Opimizaion wih Topology Opimizaion wih Buffe Inseion Buffe Inseion Wie sizing and spacing Pseudo Pin Noise Conol Simulaneous Buffe Inseion and Wie Sizing Pseudo Pin Assignmen unde Wie Noise sizing Conol and spacing Simulaneous Topology Consucion Simulaneous Buffe wih Inseion and Wie Sizing Ineconnec Layou and Wie Sizing Roue Planning Simulaneous Topology Consucion Poin-o-Poin Gidless Rouing wih Buffe Inseion and Wie Sizing Poin-o-Poin Gidless Rouing Final Layou

Cossalk Noise Aggesso ne C x Vicim ne Volage Spike (V) 0.6 0.4 0.2 0 0 0.5.5 2 2.5 Time (ns) Peious Woks Tansmission line equaions [Sakuai+, TED 93, ASPDAC 98] Only handle fully coupled bus lines Degan s model [ICCAD 97] Elegan, Elmoe-like fomula fo peak noise Oe esimaion, esp. when aggesso slew is small => could lead o noise een lage han Vdd! Chage-shaing based (e.g., [Vial & Maek-Sodawska, TCAD 97]) One lumped R, C fo icim/aggesso ne Simple noise fomulae fo peak noise, and noise ampliude -widh poduc Canno diffe nea-souce esus nea-sink coupling Need simple ye accuae model ha consides moe KEY (bu no moe han necessay) paamees o guide layou opimizaion!

2-p Cossalk Noise Model [Cong-Pan-Sinias, SRC Techcon 00, TAU 00] Aggesso ne C x Vicim ne Ls Lc Le Cl T Rd Rs Re Cs Cs2 Ce Ce2 Cl 2-p Model Rd Rs T Re Cs Cs2 Ce Ce2 Cl Rd Rs Re C=Cs C2=Cs2+Ce CL=Ce2+Cl

Closed-Fom Soluions Peak noise = x e / max + = widh e e / / 2 ln Le e 2 R ) )( ( ) ( C C R C C Cx R R C R R d L s d x s d x + + + + + = + = x : RC delay fom upseam esisance imes coupling cap. : Elmoe delay of he icim ne Noise widh Noise widh Unified View fo Exising Models Peak noise = x e / max As x max 0, hen (Vial+ TCAD 97 model) As x >> max, hen (Degan ICCAD 97 model) (2-p model) 2 2 2 / max x x x x e + = + + = = L As (Vial+ TCAD 99 model, Up o 00% lage han Degan meic fo lage )

Expeimenal Resuls,000 andom nes based on ealisic paamees Aeage Eo (%) Aeage Eo (%) Pecenage 700 600 500 400 300 200 00 0 degan ial 2-Pi Model Pecenage 8 6 4 2 0 8 6 4 2 0 ial Model 2-Pi Applicaions of 2-p Model We hae obained a se of ules fo noise educion using diffeen ineconnec opimizaions Die sizing Nea souce esus sink coupling Shield inseion Wie sizing and spacing AW poduc (noise ampliude widh) Used in Magma s BlasFusion sofwae -- U.S. Paen Pending

Accomplishmens and Ongoing Woks in Yea 3 An impoed cossalk model wih applicaion o noise consained ineconnec opimizaion. [Cong-Pan-Sinias, SRC Techcon 00, TAU 00] Pseudo pin assignmen wih cossalk noise conol [Chang-Cong, ISPD 00] Rouing ee consucion unde fixed buffe locaions [Cong-Yuan, DAC 00] Ongoing sudies on physical planning Oeiew of Ineconnec-Cenic IC Design Flow Achiecue/Concepual-leel Design Design Specificaion HDM Ineconnec Planning Physical Hieachy Geneaion Fooplan/Coase Placemen wih Ineconnec Planning Ineconnec Achiecue Planning Ineconnec Pefomance Esimaion Models (IPEM) OWS, SDWS, BISWS Sucue iew Funcional iew Physical iew Timing iew Synhesis and Placemen unde Physical Hieachy Ineconnec Synhesis Pefomance-dien Global Rouing Pseudo Pin Assignmen unde Noise Conol Ineconnec Layou Roue Planning absacion Ineconnec Opimizaion (TRIO) Topology Opimizaion wih Buffe Inseion Wie sizing and spacing Simulaneous Buffe Inseion and Wie Sizing Simulaneous Topology Consucion wih Buffe Inseion and Wie Sizing Poin-o-Poin Gidless Rouing Final Layou

Pseudo Pin Assignmen wih Cossalk Noise Conol Vias: 6 Vias: 8 Coupling: 4 Coupling: 2 Pseudo pin: a poin whee a ne cosses a ile bounday Pseudo pin assignmen: bidge beween global ouing and deailed ouing Ou conibuions: Pseudo pin assignmen algoihm fo gidless geneal aea ouing wih noise conol Conol cossalk noise Handle obsacle consains Align pseudo pins fo deailed ouing ouabiliy Reduce he oal wie lengh Why Cossalk Noise Conol in Pseudo Pin Assignmen Wha can we do in ouing o affec cossalk? Buffe inseion (if he global oue does i) Wie odeing Wie spacing Deemine wie odeing and spacing Global ouing? High complexiy, had o conside obsacles Deailed ouing? Flexibiliy is low Pseudo pin assignmen? Reasonable complexiy and high accuacy

PPA Algoihm Oeiew One laye a a ime Opimize one ow a a ime Maximum sip bounday decomposiion: Paiion bounday o ineals Deailed assignmen wihin each sip : Deemine pseudo pin locaions Coase pseudo pin assignmen: Assign pseudo pins o ineals A Noise Disibuion Example Afe Deailed Rouing 4500 4000 3500 3000 2500 nes 2000 500 000 500 0 0-0. 0.- 0.2 0.2-0.3 0.3-0.4 noise (Vdd) 0.4-0.5 no noise conol wih noise conol Tes case: scaled mcc2, NTRS 97 0.8 um Tech, 0.3 Vdd noise consains Pseudo pin assignmen wih noise conol effeciely educe cossalk noise and mee noise consains

RMP (Recusiely Meging and Puning) Algoihm Basic Idea: A boom-up ee consucion combined wih buffe inseion. Geneae a se of subees fom sinks and hen gadually expand and mege hem unil a complee ee wih bes pefomance is poduced. Key diffeences fom peious appoaches The ses of subees may no be disjoin Muliple subees may be geneaed a a node Woks on a ouing gaph Handle muliple-pin nes wih fixed buffe locaions consains. Compaison Beween RMP and Modified BA-ee Algoihm Modify BA-ee algoihm [TRIO] o handle fixed buffe inseion (MBA-ee) Simila o he semi-auomaic appoach used in eal design: ound ideal buffes in BA-ee o he gien buffes in MBA-ee. Expeimenal esuls of RMP s. BMA-ee (all daa ae nomalized wih espec o RMP). #pins 4 5 6 a.0.0.0 RMP wl.0.0.0 MBA-ee (adjacen NR) a wl.62.99.84 0.90 0.90 0.85 MBA-ee (-adjacen NR) a wl.29.46.29.08.3 0.97 RMP can oupefom MBA-ee by up o 50% in ems of delay wih compaable wielengh.

Example of Logic Hieachy in Final Layou By couesy of IBM (Tony Dumm) Example of Logic Hieachy in Final Layou By couesy of IBM (Tony Dumm)

Seeal Ongoing Effos Sudies on he impacs of laye assignmen Sudies on he congesion of global ineconnec A easonable fomulaion fo physical planning Impacs of Laye Assignmens on Delays delay (ps) 600 400 200 000 800 600 400 200 0 0.5 3.5 6.5 laye -2 laye 3-4 laye 5-6 laye 7-8 9.5 2.5 5.5 8.5 2.5 24.5 27.5 Delays esimaed by IPEM fo opimal buffe inseion and wie sizing 0.3 um NTRS 97 echnology Delay educion of changing wies fom layes -2 o layes 7-8: 0.5mm: 2% 6.5mm: 40% 27.5mm: 49% The longe he wie, he moe possible educion by assigning o uppe meals wie lengh (mm)

Seeal Ongoing Effos Sudies on he impacs of laye assignmen Sudies on he congesion of global ineconnec A easonable fomulaion fo physical planning Congesion Analysis Effos and Peliminay Resuls Uppe meal layes ae used fo long wies fo educing delays Ae hee enough ouing esouce on uppe meal layes? Wha is he end? How many long wies ha need o be oued on uppe meal layes? How much space aailable on uppe meal layes (Powe and Clock nes ae also compeing)? Lis of indusial conacs ha we consuled: IBM Tony Dumm, John Dainge Inel Desmond Kikpaick, Mosu Mohan, Kis Konigsfeld HP Noman Chang

Laye Compeiion unde Diffeen Tage Delays (Tes case fom IBM) Wie aea equiemens unde diffeen age delays using IPEM wih 0.3um NTRS'97 Tech aea 350 300 250 200 50 00 50 0 00 200 300 400 500 600 700 800 900 age delay(ps) 000 delay no mee laye 7-8 o aboe laye 5-6 o aboe laye 3-4 o aboe laye -2 o aboe Seeal Ongoing Effos Sudies on he impacs of laye assignmen Sudies on he congesion of global ineconnec A easonable fomulaion fo physical planning

Poblem Fomulaion fo Physical Planning Plan he following o achiee opimizaion goals: Physical hieachy wih ough geomeic infomaion fo idenifying global ineconnecs Reiming and pipelining Laye assignmen fo global ineconnecs Global ne opology geneaion and congesion conol Buffe planning Esimae and Opimize he following objecies: Delay Aea Powe Signal inegiy Delieables Deelopmen of efficien and accuae ineconnec pefomance esimaion models fo ineconnec-dien synhesis and planning (Compleed - 30-Jun-999) Deelopmen of ineconnec achiecue planning famewok (Compleed - 30-Jun-999) Deelopmen of efficien algoihms fo inegaed ineconnec planning & flooplanning capabiliies a he physical leel (Compleed - 30-Sep-999) Deelopmen & alidaion of accuae noise models o guide he ineconnec synhesis algoihm fo signal eliabiliy (Compleed - 3-Dec-999) Deelopmen of opimal o nea -opimal ineconnec synhesis algoihm fo muliple spaially o empoally elaed signal nes fo pefomance & signal eliabiliy opimizaion (Compleed - 3- Dec-999) Deelopmen of efficien algoihms fo inegaed ineconnec planning & flooplanning capabiliies a he RTL-leel; Sofwae (Planned - 3-Dec-2000)

Technology Tansfe TRIO (Tee-Repeae-Ineconnec-Opimizaion) package Inegaed ino Inel design echnology hp://cadlab.cs.ucla.edu/~io IPEM (Ineconnec Pefomance Esimaion Model) package Inegaed ino IBM design echnology hp://cadlab.cs.ucla.edu/sofwae_elease/ipem/hdocs Wie widh planning U.S. Paen pending unde SRC sponsoship BBP (Buffe Block Planning) fo physical leel flooplanning Souce code ansfeed o IBM Ineess fom Inel and HP Cossalk noise modeling U.S. Paen pending (join wih Magma) Summay An impoed cossalk model wih applicaion o noise consained ineconnec opimizaion. Pseudo pin assignmen wih cossalk noise conol Rouing ee consucion unde fixed buffe locaions Ongoing sudies on physical planning

Milesones Deelopmen of a compuaional model fo ineconnec achiecue planning based on a gien design chaaceizaion (specified in ems of age clock ae, ineconnec disibuion, dephs of logic,newok, ec.) (3-Dec-998) Deelopmen of esimaion models fo ineconnec layou opimizaions suiable fo pe-layou synhesis and planning (3-Dec-998) Deelopmen of efficien algoihms fo inegaed ineconnec planning and flooplanning capabiliies a he RTL-leel (3-Dec-999) Compleion of he ongoing effo on he deelopmen on a muli -laye geneal-aea gidless ouing sysem (3-Dec-999) Deelopmen of opimal o nea-opimal ineconnec synhesis algoihm fo muliple spaially o empoally elaed signal nes fo pefomance and signal eliabiliy opimizaion (3-Dec-999) Deelopmen and alidaion of ey efficien bu accuae noise models o elae he noise wih he physical paamees o guide he ineconnec synhesis algoihm fo signal eliabiliy opimizaion (3-Dec-999) Deelopmen of efficien algoihms fo inegaed ineconnec planning and flooplanning capabiliies a he physical leel (3-Dec-999) Deelopmen of efficien algoihms fo inegaed ineconnec planning and flooplanning capabiliies a he RT-leel (3-Dec-2000)