DRIVER, DC - GHz Typical Applications The is ideal for: Gbps NRZ MZ & Low V Π Modulator Driver Gbps RZ Transmission 4 Gbps DQPSK Broadband Gain Block for Test & Measurement Equipment Military & Space Functional Diagram Features Wide Supply Range from 3.3V to 7V Adjustable Output Amplitude: 2. to 8 Vp-p Low Additive RMS Jitter, <3 fs Low DC Power Consumption 1W for Vout = 8 Vp-p at Vdd = 7V Cross Point Adjustment 32 Lead xmm SMT Package: 2mm² General Description The is a GaAs MMIC phemt Distributed Driver Amplifier packaged in a leadless x mm surface mount package which operates between DC and GHz. The amplifier provides 17 of gain, 8Vp-p saturated output swing and features output swing cross point adjustment. Gain flatness is excellent at ±. as well as very low additive RMS jitter of 3 fs for Gbps operation. provides Metro and Long Haul designers with scalable power dissipation for varying output drive requirements. (<.4W at Vout = 3.6 Vp-p and <1W at Vout = 8. Vp-p) The has a very wide supply (Vdd) operating range from +3.3V to +7V, and the RF I/Os are internally matched to Ohms. Electrical Specifications, T A = +2 C, Vdd = 7V, Vctl = 1V, Idd = 16mA* Gain Parameter Conditions Min. Typ. Max. Units Frequency = 1-8 GHz Frequency = 8-16 GHz Frequency = 16 - GHz Small Signal Bandwidth 3- cutoff GHz Input Return Loss Output Return Loss Gain Variation over Temperature Frequency = 1 - GHz Frequency = - GHz Frequency = 1 - GHz Frequency = - GHz Frequency = 1 - GHz Frequency = - GHz Group Delay Variation Frequency = 1-12 GHz ± ps Saturated Output Power (Psat) * Adjust Vgg between -2V to V to achieve Idd= 16 ma typical. Frequency = 1-12 GHz Frequency = 12 - GHz 14 13 12 17. 16. 16..32 24 23.2.4 / C / C m m 1
DRIVER, DC - GHz Electrical Specifications, T A = +2 C, Vdd = 7V, Vctl = 1V, Idd = 16mA* Continued Output Power for 1 Compression (P1) Parameter Conditions Min. Typ. Max. Units Frequency = 1-12 GHz Frequency = 12 - GHz Rise Time [1] % - 8% ps Fall Time [1] % - 8% ps Additive RMS Jitter [2] 3 fs Supply Current (Idd) (Vgg = -.6V Typ.) 16 ma Bias Current Adjust (Vgg) -2 V Output Voltage Adjust (Vctl) 2 V [1] Data input = 22. Gbps NRZ PRBS 2 23-1 pattern, 1.2 Vp-p. [2] RMS jitter is calculated with 22. Gbps 1... pattern. * Adjust Vgg between -2V to V to achieve Idd = 16 ma typical. Electrical Specifications, T A = +2 C, Vdd = V, Vctl = 1V, Idd = 14mA* Gain Parameter Conditions Min. Typ. Max. Units Frequency = 1-8 GHz Frequency = 8-16 GHz Frequency = 16 - GHz Small Signal Bandwidth 3- cutoff GHz Input Return Loss Output Return Loss Gain Variation over Temperature Frequency = 1 - GHz Frequency = - GHz Frequency = 1 - GHz Frequency = - GHz Frequency = 1 - GHz Frequency = - GHz Group Delay Variation Frequency = 1-12 GHz ± deg Saturated Output Power (Psat) Output Power for 1 Compression (P1) Frequency = 1-12 GHz Frequency = 12 - GHz Frequency = 1-12 GHz Frequency = 12 - GHz Rise Time [1] % - 8% ps Fall Time [1] % - 8% ps Additive RMS Jitter [2] 3 fs Supply Current (Idd) (Vgg = -.6V Typ.) 14 ma Bias Current Adjust (Vgg) -2 V Output Voltage Adjust (Vctl) 2 V [1] Data input = 22. Gbps NRZ PRBS 2 23-1 pattern, 1.2 Vp-p. [2] RMS jitter is calculated with 22. Gbps 1... pattern. * Adjust Vgg between -2V to V to achieve Idd = 14 ma typical. 19 18 14 13. 12 18 17 22 21 17. 17. 16..16.29 22. 22..2.4 m m / C / C m m m m 2
DRIVER, DC - GHz Gain & Return Loss @ Vdd = 7V 2 Gain & Return Loss @ Vdd = V 2 RESPONSE () - - -2 S21 S11 S22-3 4 8 12 16 Gain & Return Loss @ Vdd = 3.3V RESPONSE () 2 - - -2 S21 S11 S22-3 4 8 12 16 RESPONSE () - - -2-3 4 8 12 16 Gain vs. Temperature @ Vdd = 7V GAIN () 2 S21 S11 S22 +2C +8C 4 8 12 16 Gain vs. Temperature @ Vdd = V 2 Gain vs. Temperature @ Vdd = 3.3V 2 GAIN () +2C +8C GAIN () +2C +8C 4 8 12 16 4 8 12 16 3
DRIVER, DC - GHz P1 vs. Temperature @ Vdd = 7V 3 Psat vs. Temperature @ Vdd = 7V 3 P1 (m) 27 24 21 18 +2C +8C 4 8 12 16 Output Power vs. Input Power @ GHz, Vdd = 7V OUTPUT POWER (m) 28 24 16 12 8-6 -4-2 2 4 6 8 12 14 INPUT POWER (m) Output Power vs. Input Power @ GHz, Vdd = 3.3V 28 +2C +8C PSAT (m) 27 24 21 18 +2C +8C 4 8 12 16 Output Power vs. Input Power @ GHz, Vdd = V OUTPUT POWER (m) 28 24 16 12 +2C +8C 8-6 -4-2 2 4 6 8 12 14 INPUT POWER (m) Peak-to-Peak Output Voltage vs. Vdd @ 11.2 Gbps [1] OUTPUT POWER (m) 24 16 12 +2C +8C P-P OUTPUT VOLTAGE (Vp-p) 8 6 4 2 Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V 8-6 -4-2 2 4 6 8 12 INPUT POWER (m).1.2.3.4..6.7.8.9 1 [1] Data input = 11.2 Gbps NRZ PRBS 2 23-1 pattern, 1.2 Vp-p. 4
Peak-to-Peak Output Voltage vs. Vdd @ 22. Gbps [1] DRIVER, DC - GHz Rise Time vs. Vdd @ 22. Gbps [1] 2 P-P OUTPUT VOLTAGE (Vp-p) 8 6 4 2 Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V.1.2.3.4..6.7.8.9 1 Fall Time vs. Vdd@ 22. Gbps [1] FALLTIME (ps) 2 Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V.1.2.3.4..6.7.8.9 1 RISE TIME (ps) Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V.1.2.3.4..6.7.8.9 1 RMS Jitter vs. Vdd @ 22. Gbps [2] RMS JITTER (fs) 3 2 Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V.1.2.3.4..6.7.8.9 1 Peak-to-Peak Jitter vs. Vdd @ 11.2 Gbps [3][4] Peak-to-Peak Jitter vs. Vdd @ 22. Gbps [1][4] P-P JITTER (ps) Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V P-P JITTER (ps) Vdd=3.3V Vdd=V Vdd=6V Vdd=7V.1.2.3.4..6.7.8.9 1.1.2.3.4..6.7.8.9 1 [1] Data input = 22. Gbps NRZ PRBS 2 23-1 pattern, 1.2 Vp-p. [2] RMS jitter is measured with 22. Gbps 1... pattern. [3] Data input = 11.2 Gbps NRZ PRBS 2 23-1 pattern, 1.2 Vp-p. [4] Source jitter was not de-embedded.
DRIVER, DC - GHz Supply Current vs. Vdd @ 22. Gbps [1] Noise Figure vs. Temperature @ Vdd = 7V 6 SUPPLY CURRENT (ma) 16 1 8 Vdd = 3.3V Vdd = V Vdd = 6V Vdd = 7V 4.1.2.3.4..6.7.8.9 1 [1] Data Input = 22. Gbps NRZ PRBS 223-1 pattern, 1.2 Vp-p 11.2 Gbps NRZ Output Eye Diagram NOISE FIGURE () 4 3 2 1 +2C +8C 2 4 6 8 12 14 16 18 Measurements Current Min Max Units Eye Amplitude 3.6 3.6 3.6 V Rise Time ps Fall Time 21.33.67 22 ps Jitter RMS 1.893 1.87 2.72 ps Time scale: 3. ps/div Amplitude scale: 762 mv/div Vdd = 3.3V, Vin: 11.2 Gbps NRZ PRBS 2 31-1,. Vp-p Vout: 3.6Vp-p Vctl = 1V 11.2 Gbps NRZ Output Eye Diagram Measurements Current Min Max Units Eye Amplitude 7.47 7.47 7.47 V SNR 17.97 17.88 18.12 V/V Time scale: 3. ps/div Amplitude scale: 1.17 V/div Vdd = V, Vin: 11.2Gbps NRZ PRBS 2 31-1, 1.2V p-p, Vout: 7.Vp-p Vctl = 1V 6
DRIVER, DC - GHz 11.2 Gbps NRZ Output Eye Diagram (Continued) 22. Gbps NRZ Output Eye Diagram Measurements Current Min Max Units Eye Amplitude 8.26 8.26 8.27 V SNR 22.3 22.26 22.1 V/V Time scale: 3. ps/div Amplitude scale: 1.17 V/div Vdd = 7V, Vin: 11.2Gbps NRZ PRBS 2 31-1, 1.2V p-p, Vout: 8.3Vp-p Vctl = 1V Measurements Current Min Max Units Eye Amplitude 3.3 3.3 3.4 V Rise Time 18.22 17.33 18.22 ps Fall Time.44 19.6.89 ps Jitter RMS 2.417 2.187 2.422 ps Time scale:. ps/div Amplitude scale: 762 mv/div Vdd = 3.3V, Vin: 22.Gbps NRZ PRBS 2 31-1,.V p-p, Vout: 3.Vp-p Vctl = 1V 22. Gbps NRZ Output Eye Diagram Measurements Current Min Max Units Eye Amplitude 7.8 7.84 7.8 V SNR 13.74 13.69 14.7 V/V Time scale:. ps/div Amplitude scale: 1.17 V/div Vdd = 7V, Vin: 22.Gbps NRZ PRBS 2 31-1, 1.2 V p-p, Vout: 7.9Vp-p Vctl = 1V 7
DRIVER, DC - GHz 11.2 Gbps RZ Output Eye Diagram 11.2 Gbps RZ Output Eye Diagram Measurements Current Units Jitter RMS 1.93 ps Bit Rate 11.2 Gb/s Time scale: 4. ps/div Amplitude scale: 1.22 V/div Vdd = 3.3V, Vin: 11.2Gbps RZ PRBS 2 31-1,.3V p-p, Vout: 2.9Vp-p Vctl = 1V Measurements Current Min Max Units Duty Cycle 1..4 7.1 % SNR.8 13.3.96 V/V Jitter RMS 1.73 1.689 1.79 ps Eye Amplitude 2.8 2.37 2.86 V Time scale: 3. ps/div Amplitude scale: 647 mv/div Vdd = V, Vin: 11.2Gbps RZ PRBS 2 31-1, 1.2V p-p, Vout: 6Vp-p Vctl = 1V Absolute Maximum Ratings Drain Bias Voltage (Vdd) +9V Gate Bias Voltage (Vgg) Control Bias Voltage (Vctl) RF Input Power (RFIN)(Vdd = +7 Vdc) -2V to V (Vdd -7) to Vdd (V) +23 m Channel Temperature 17 C Continuous Pdiss (T = 8 C) (derate 24 mw/ C above 8 C) Thermal Resistance (channel to ground paddle) 1. W 9.4 C/W Storage Temperature -6 to + C Operating Temperature -4 to +8 C ESD Sensitivity (HBM) Class 1A Typical Supply Current vs. Vdd* Vdd (V) Idd (ma)* Power Dissipation (W) +3.3.33 +. 14.7 +6. 16.96 +7. 16 1.1 * Adjust Vgg between -2V to V to achieve Idd shown. ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS 8
DRIVER, DC - GHz Outline Drawing NOTES: 1. PACKAGE BODY MATERIAL: ALUMINA 2. LEAD AND GROUND PADDLE PLATING: 3-8 MICROINCHES GOLD OVER MICROINCHES MINIMUM NICKEL. 3. DIMENSIONS ARE IN INCHES [MILLIMETERS]. 4. LEAD SPACING TOLERANCE IS NON-CUMULATIVE.. PACKAGE WARP SHALL NOT EXCEED.mm DATUM -C- 6. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. Package Information Part Number Package Body Material Lead Finish MSL Rating Package Marking [2] [1] H87 Alumina, White Gold over Nickel MSL3 XXXX [1] Max peak reflow temperature of 26 C [2] 4-Digit lot number XXXX 9
DRIVER, DC - GHz Pin Descriptions Pin Number Function Description Interface Schematic 1, 3, 4, 7-12, 14, 17-19, 22-28, 31, 32 N/C 2 Vctl RFIN 6, GND The pins are not connected internally; however, all data shown herein was measured with these pins connected to RF/DC ground externally. Output voltage swing adjustment. +1V should be applied to Vctl for nominal operation. This pin is DC coupled and matched to Ohms. RF/DC Ground. These pins and the package base must be connected to RF/DC ground. 13 Vgg Gate Control for amplifier. ACG4 16 ACG3 21 RFOUT & Vdd 29 ACG2 3 ACG1 Low frequency termination. Attach bypass capacitor per application circuit herein. RF output for amplifier. Connect the DC bias (Vdd) network to provide drain current (Idd). See application circuit herein. Low frequency termination. Attach bypass capacitor per application circuit herein.
DRIVER, DC - GHz Application Circuit NOTE 1: Drain Bias (Vdd) must be applied through a broadband bias tee or external bias network. 11
DRIVER, DC - GHz Evaluation PCB List of Materials for Evaluation PCB 8347 [1] Item J1 - J2 J3 - J4 Description PCB Mount SMA Connector 2mm Molex Header C1, C2 pf Capacitor, 42 Pkg. C3 - C6 C7 - C9 U1 PCB [2] pf Capacitor, 63 Pkg. 4.7 µf Capacitor, Tantalum, Modulator Driver 976 Evaluation PCB [1] Reference this number when ordering complete evaluation PCB [2] Circuit Board Material: Arlon 2FR or Rogers 43 The circuit board used in the application should use RF circuit design techniques. Signal lines should have Ohm impedance while the package ground leads and package bottom should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation board should be mounted to an appropriate heat sink. The evaluation circuit board shown is available from Hittite upon request. 12
DRIVER, DC - GHz Device Operation These devices are susceptible to damage from Electrostatic Discharge. Proper precautions should be observed during handling, assembly and test. The input to this device should be AC-coupled. To provide the typical 8Vp-p output voltage swing, a 1.2Vp-p AC-coupled input voltage swing is required. Device Power Up Instructions 1. Ground the device 2. Set Vgg to -2V (no drain current) 3. Set Vctl to +1V (no drain current) 4. Set Vdd to +V (no drain current). Adjust Vgg for Idd = 14mA Vgg may be varied between -1V and V to provide the desired eye crossing point percentage (i.e. % crosspoint) and a limited cross point control capability. Vdd may be increased to +7V if required to achieve greater output voltage swing. Vctl may be adjusted between +2V and +V to vary the output voltage swing. Device Power Down Instructions 1. Reverse the sequence identified above in steps 1 through 4. 13
DRIVER, DC - GHz 14