FDMB2307NZ Dual Common Drain N-Channel PowerTrench MOSFET

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FDMB237NZ Dual Common Drain N-Channel PowerTrench MOSFET 2 V, 9.7 A, 6.5 mω Features Max r SS2(on) = 6.5 mω at V GS = 4.5 V, I D = 8 A Max r SS2(on) = 8 mω at V GS = 4.2 V, I D = 7.4 A Max r SS2(on) = 2 mω at V GS = 3. V, I D = 7 A Max r SS2(on) = 24 mω at V GS = 2.5 V, I D = 6.7 A Low Profile -.8 mm maximum - in the new package MicroFET 2x3 mm HBM ESD protection level > 2 kv (Note 3) RoHS Compliant Pin Pin S D/D2 S G General Description April 24 This device is designed specifically as a single package solution for Li-Ion battery pack protection circuit and other ultra-portable applications. It features two common drain N-channel MOSFETs, which enables bidirectional current flow, on Fairchild s advanced PowerTrench process with state of the art MicroFET Leadframe, the FDMB237NZ minimizes both PCB space and r SS2(on). Application Li-Ion Battery Pack G2 S2 S2 4 3 5 6 2 G S S S2 S2 G2 Top Bottom MLP 2x3 MOSFET Maximum Ratings T A = 25 C unless otherwise noted Symbol Parameter Ratings Units V SS2 Source to Source2 Voltage 2 V V GS Gate to Source Voltage (Note 4) ±2 V Source to Source2 Current -Continuous T A = 25 C (Note a) 9.7 I SS2 -Pulsed 4 A Power Dissipation T A = 25 C (Note a) 2.2 P D Power Dissipation T A = 25 C (Note b).8 W T J, T STG Operating and Storage Junction Temperature Range -55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction to Ambient(Dual Operation) (Note a) 57 R θja Thermal Resistance, Junction to Ambient(Dual Operation) (Note b) 6 Package Marking and Ordering Information C/W Device Marking Device Package Reel Size Tape Width Quantity 37 FDMB237NZ MLP 2x3 7 8 mm 3 units

Electrical Characteristics T J = 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics I SS2 Zero Gate Voltage Source to Source2 Current V SS2 = 6 V, V GS = V μa I GSS Gate to Source Leakage Current V GS = 2 V, V SS2 = V μa On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V SS2, I SS2 = 25 μa.6.5 V Dynamic Characteristics Switching Characteristics V GS = 4.5 V, I SS2 = 8 A.5 3.5 6.5 V GS = 4.2 V, I SS2 = 7.4 A 4 8 V r SS2(on) Static Source to Source2 On Resistance GS = 3. V, I SS2 = 7 A.5 6 2 mω V GS = 2.5 V, I SS2 = 6.7 A 2 8 24 V GS = 4.5 V, I SS2 = 8 A, 2 29 T J = 25 C g FS Forward Transconductance V SS2 = 5 V, I SS2 = 8 A 4 S C iss Input Capacitance 76 264 pf V SS2 = V, V GS = V, C oss Output Capacitance 229 345 pf f = MHz C rss Reverse Transfer Capacitance 2 32 pf R g Gate Resistance (Note 5). 2.6 8 Ω t d(on) Turn-On Delay Time 2 22 ns t r Rise Time V SS2 = V, I SS2 = 8 A, 9 34 ns t d(off) Turn-Off Delay Time V GS = 4.5 V, R GEN = 6 Ω 32 5 ns t f Fall Time 9.5 7 ns Q g Total Gate Charge V GS = V to 5 V 2 28 nc Q V SS2 = V, g Total Gate Charge V GS = V to 4.5 V 8 25 nc I SS2 = 8 A, Q gs Gate to Source Charge 2.8 nc V G2S2 = V Q gd Gate to Source2 Miller Charge 5.3 nc Source- Source2 Diode Characteristics I fss Maximum Continuous Source-Source2 Diode Forward Current 8 A V fss Source to Source2 Diode Forward Voltage V GS = V, V G2S2 = 4.5 V,.8.2 V I fss = 8 A (Note 2) NOTES:. R θja is determined with the device mounted on a in 2 pad 2 oz copper pad on a.5 x.5 in. board of FR-4 material. R θjc is guaranteed by design while R θca is determined by the user's board design. a. 57 C/W when mounted on a in 2 pad of 2 oz copper b. 6 C/W when mounted on a minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 3 μs, Duty cycle < 2.%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 5. Rg is measured on % of the die at wafer level. 2

Typical Characteristics T J = 25 C unless otherwise noted ISS2, SOURCE TO SOURCE2 CURRENT (A) NORMALIZED SOURCE TO SOURCE2 ON-RESISTANCE 4 3 2..2.4.6.8 V SS2, SOURCE TO SOURCE2 VOLTAGE (V).5. Figure. V GS = 4.5 V V GS = 4.2 V V GS = 3. V V GS = 2.5 V V G2S2 = 4.5 V ISS2, SOURCE TO SOURCE2 CURRENT (A)..2.4.6.8 V SS2, SOURCE TO SOURCE2 VOLTAGE (V) On-Region Characteristics Figure 2. On-Region Characteristics V GS = 2.5 V V GS = 3. V V GS = 4.2 V V GS = 4.5 V V G2S2 = 4.5 V.5 2 3 4 I SS2, SOURCE TO SOURCE2 CURRENT (A) Figure 3. Normalized On-Resistance vs Source to Source2 Current and Gate Voltage NORMALIZED SOURCE TO SOURCE2 ON-RESISTANCE 4 3 2.5. V GS = 2.5 V V GS = 4.5 V V GS = 4.2 V V GS = 3. V V GS = 3. V V GS = 2.5 V V GS = 4.2 V V GS = 4.5 V.5 2 3 4 I SS2, SOURCE TO SOURCE2 CURRENT (A) Figure 4. Normalized On-Resistance vs Source to Source2 Current and Gate Voltage NORMALIZED SOURCE TO SOURCE2 ON-RESISTANCE.6.4.2..8 I SS2 = 8 A V GS = 4.5 V.6-5 -25 25 5 75 25 5 T J, JUNCTION TEMPERATURE ( o C) Figure 5. Normalized On Resistance vs Junction Temperature rss2(on), SOURCE TO SOURCE2 ON-RESISTANCE (mω) 8 6 4 2 T J = 25 o C..5 2. 2.5 3. 3.5 4. 4.5 Figure 6. T J = 5 o C I SS2 = 8 A V GS, GATE TO SOURCE VOLTAGE (V) On Resistance vs Gate to Source Voltage 3

Typical Characteristics T J = 25 C unless otherwise noted I SS2, SOURCE TO SOURCE2 CURRENT (A) VGS, GATE TO SOURCE VOLTAGE (V) 4 3 2 V SS2 = 5 V.5..5 2. 5 4 3 2 Figure 7. V G2S2 = V I SS2 = 8 A T J = 5 o C T J = 25 o C V GS, GATE TO SOURCE VOLTAGE (V) T J = -55 o C Ifss, SOURCE TO SOURCE2 FORWARD CURRENT (A)...2.4.6.8..2 Transfer Characteristics Figure 8. Source to Source2 Diode Forward Voltage vs Source Current V SS2 = 8 V V SS2 = 2 V V SS2 = V 5 5 2 25 Q g, GATE CHARGE (nc) Figure 9. Gate Charge Characteristics CAPACITANCE (pf).. V GS = V, V G2S2 = 4.5 V T J = 5 o C T J = 25 o C T J = -55 o C V fss, BODY DIODE FORWARD VOLTAGE (V) C iss C oss C rss Figure. Capacitance vs Source to Source2 Voltage f = MHz V GS = V. 2 VSS2, SOURCE TO SOURCE2 VOLTAGE (V) Ig, GATE LEAKAGE CURRENT (A) - V SS2 = V -2-3 -4-5 -6-7 -8-9 - 4 8 2 6 Figure. T J = 25 o C T J = 25 o C V GS, GATE TO SOURCE VOLTAGE (V) Gate Leakage Current vs Gate to Source Voltage ISS2, SOURCE TO SOURCE2 CURRENT (A) ms THIS AREA IS LIMITED BY r DS(on) ms SINGLE PULSE s. T J = MAX RATED s R θja = 6 o C/W DC T A = 25 o C... V SS2, SOURCE TO SOURCE2 VOLTAGE (V) Figure 2. Forward Bias Safe Operating Area ms 4

Typical Characteristics T J = 25 C unless otherwise noted P (PK), PEAK TRANSIENT POWER (W) NORMALIZED THERMAL IMPEDANCE, Z θja.5-3 -2 - t, PULSE WIDTH (sec) 2.. DUTY CYCLE-DESCENDING ORDER D =.5.2..5.2. Figure 3. Single Pulse Maximum Power Dissipation SINGLE PULSE R θja = 6 o C/W SINGLE PULSE R θja = 6 o C/W T A = 25 o C. -3-2 - t, RECTANGULAR PULSE DURATION (sec) P DM t t 2 NOTES: DUTY FACTOR: D = t /t 2 PEAK T J = P DM x Z θja x R θja + T A Figure 4. Junction-to-Ambient Transient Thermal Response Curve 5

Dimensional Outline and Pad Layout Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http:///package/packagedetails.html?id=pn_mldea-c6. 6

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Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. 7 Rev. I68

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