011 nd Powe Electonics, Dive Systems and Technologies Confeence A Novel Single-Phase Six-Switch AC/AC Convete fo UPS Applications A. Fatemi 1, Student Membe, IEEE, M. Azizi, Student Membe, IEEE, M. Shahpaasti, M. Mohamadian 3, Membe, IEEE, A. Yazdian, Membe, IEEE Powe Electonics and Potection Laboatoy (PEP Lab.), Faculty of Electical and Compute Engineeing Tabiat Modaes Univesity, P.O.Box.14115-143, Tehan, Ian. Emails: 1 a.fatemi@modaes.ac.i, m-azizi@ modaes.ac.i, 3 mohamadian@modaes.ac.i Abstact A new educed-switch-count convete topology is intoduced and poposed fo UPS applications in this pape. The modulation scheme of this novel convete is developed and a method is devised fo calculating the optimal opeating point of the convete based on the design specifications in ode to maximize dc bus voltage utilization while minimizing the output voltage THD and switching loss. Moeove, a stategy is suggested fo battey chaging peiod which inceases convete input powe and hence acceleates battey chaging pocess. The poposed convete possesses desiable chaacteistics of an ideal AC/AC convete such as low THD of input cuent and output voltage and unity powe facto. The validity of theoetical issues is confimed by simulation esults. Keywods- UPS, PWM ectifie,reduced-switch count topology, AC/AC convete, Nine-switch convete I. INTRODUCTION Uninteuptible powe supplies (UPS) ae widely used fo supplying sensitive loads such as medical facilities, telecommunications, compute systems and industial pocessing. The main objective of employing UPS systems is potecting these sensitive loads fom powe failue and netwok distotions such as voltage sag, suge and flicke [1]. Amongst diffeent types of UPS systems, one-line configuation (Fig. 1) is known to have the best pefomance consideing powe conditioning, eliability and load potection. Geat toleance to input voltage vaiation and pecise egulation of output voltage ae the most eminent advantages of this goup ove othe two common types of UPS systems which ae off-line and line-inteactive UPSs. Howeve, as it can be seen in Fig., high numbe of semiconducto devices which inceases the manufactue cost and double convesion of electic powe, AC/DC in the ectifie stage and DC/AC in the invete stage, which inceases the powe loss ae the main disadvantages of this topology []. Thee has been a ecent tend of educing total cost of online UPS systems by educing the numbe of switches employed in thei stuctue. The hitheto poposed solutions fo switch eduction in on-line UPS systems can be categoized into two geneal goups: The fist appoach is based on using Half-bidge convetes instead of two back-to-back connected Full-bidge cells (Fig. 3). Numbe of switches will be educed in this way by half. Howeve, this method lowes the dc bus utilization such that to AC DC AC DC Fig. 1. Block diagam of on-line UPS system supply the same load, the dc bus voltage level should be twice as much, in compaison with full bidge convetes. This esults in highe numbe of batteies in the battey bank and hence inceases the total cost of the system [3]. To alleviate this poblem, [4] poposed using a bidiectional convete in the battey cicuit which also boosts the battey voltage when it is supplying the load (Fig. 4). This solution sophisticates the contol cicuit and, simila to [5], is unable to compensate the input souce voltage dop [6]. The othe appoach to switch eduction of on-line UPS systems is based on meging the two stages of powe convesion into one. Specifically, the poposed convete in [6] (Fig. 5), and in geneal the AC/AC convetes which shae one o two legs between the invete and the ectifie stage use this concept [7]. A ecent stuctue poposed in [8] and investigated in [9,10] also employs the concept of AC/DC powe coalescence by combining the invete and ectifie stages via shaing not an entie leg but an entie ow of switches fo thee-phase invetes (Fig. 6). Howeve, due to highe voltage stess and switching loss in compaison with Full-bidge back-to-back convetes, this topology is moe suitable fo low voltage and low powe applications. In this pape this novel idea of shaing switches in powe convetes is applied to single-phase convetes which ae moe common in domestic applications with low voltage and powe atings. Simila to the thee-phase configuation, single-phase topology has two modes of opeation: equal fequency (EF) and diffeent fequency (DF). In [11], it is claimed that the EF mode is the most suitable mode of opeation fo UPS systems 978-1-6184-41-3/11/$6.00 011 IEEE 408
Fig.. Full-bidge back-to-back convete Fig. 3. Half-bidge back-to-back convete Fig. 4. Half-bidge back-to-back convete fo UPS Rectifie Stage Q1 Q4 Souce Shaed Switches Q Q5 Filte & Load Invete Stage Q3 Q6 Fig. 5. Thee-leg type single-phase convete Fig. 6. Nine-switch thee-phase convete Fig. 7 Poposed single-phase convete consideing the output voltage THD, switching loss and DC bus utilization. But this means a non-isolated-fequency UPS system. Output fequency egulation is especially impotant in weak utility systems. To gain the most possible DC bus utilization as well as egulation of the output fequency, a stategy is poposed in this pape fo using in UPS applications. This stategy consists of an optimal opeating point fo nomal opeation and a battey chaging stategy afte backup mode is finished fo maximum battey chaging pace. The poposed topology enjoys the benefits of an ideal single-phase AC/AC convete such as low THD input cuent, unity powe facto, fast dynamic esponse and the ability to compensate input voltage dop when supplying linea o nonlinea loads. The pape is oganized into seven sections. Next section, intoduces the new topology and the modulation scheme developed fo it. P-q theoy which was employed fo contolling the poposed convete is biefly explained in section thee. Section fou yields the necessay equations fo obtaining optimal opeating point. The poposed stategy fo battey chaging is expanded in section five. Section six and seven ae dedicated to simulation esults and conclusion. II. THE PROPOSED STRUCTURE AND MODULATION SCHEME Fig. 7 shows the stuctue of the poposed convete. Integating invete and ectifie legs, the poposed stuctue consists of two legs with thee semiconducto devices in each one. The middle switches ae shaed between the invete and ectifie. The numbe of employed switches is educed by 5% compaed to the common back-to-back convetes. The modulation scheme of this convete is obtained by combining the unipola PWM modulation scheme of singlephase H-bidge invetes and the modulation scheme of nineswitch convetes. The unipola modulation nomally equies two sinusoidal modulating waves, one pe leg, of the same magnitude and fequency but 180 out of phase. These waves ae then compaed with a caie signal to geneate gate signals. Nine-switch convete modulation scheme adds an offset to the two efeence signals of each leg to povide fequency and/o amplitude independency fo the outputs. The value of this offset is dependent upon the convete mode of opeation. A. Equal Fequency mode of opeation In this mode, output and input fequencies ae equal. If the efeences ae in-phase, fo optimal switching modulation, the offset is detemined by (1) in which M 1 and M could be eithe ectifie o invete modulation indices and could be inceased up to one [1]. If the efeences ae phase-shifted, the condition () should be met and no offset should be added. if M offset1= 0 > M = offset = M M 1 1 M 1 sin( ωt θ) 1 M 1 M sin ωt M 1 () (1) 409
B. Diffeent Fequency mode of opeation This mode of opeation povides fequency and amplitude independency of invete and ectifie stages by splitting the total modulation index between them. Adding offsets of 0.5 and -0.5 to ectifie and invete efeences and esticting thei amplitudes to less than half, gives the pope modulating signals. As Fig. 8 shows, to obtain the modulating signal of the poposed convete, the ectifie and invete efeence wavefoms and thei negative values should be shifted up o down with the appopiate offset consideing DF o EF opeation. This geneates the modulating signal of the uppe and lowe switches. The switching signals of the middle switches ae the logical XOR of the uppe and lowe gate signals of the same leg switches. Offset_Rec θ θ V ef _ ec V ef _ inv -1 Offset_Inv -1 Caie Fig. 8. Block diagam of signal geneation unit III. CONTROL OF THE PROPOSED CONVERTER Since the modulation signals of the invete and ectifie stages ae poduced independently, all the existing methods of contolling the dc bus voltage in one-phase ectifies ae applicable to the poposed stuctue. The method employed hee is based on single-phase p-q theoy poposed in [13]. Its block diagam is shown in Fig. 9. The advantages of this method ae constant switching fequency, low THD of input cuent, fast dynamic and unity powe facto. Fist by using (3), and imaginay component of the feedback vaiable is ceated which lags the eal signal by 90 o. ssr = ssm sin( ωt φ) π ssim = ssmsin( ωt φ ) Using these two signals and (4), the feedback vaiable will be tansfomed to d-q plane; efeence values of V * * d and V q ae obtained by indiectly contolling injected active/eactive powe to the system with the aim of contolling dc bus voltage. sd sinθ cosθ ssr s = d cosθ sinθ s (4) SIm IV. PROPOSED OPERATING POINT FOR THE CONVERTER As mentioned ealie, the poposed stuctue has two modes of opeation, EF and DF mode. The main dawback of EF mode is fequency-dependency between the ectifie and invete stages. This dependency disables the system fom Q1 Q4 Q5 Q Q3 Q6 (3) Fig. 9. Block diagam of the contol unit egulating output fequency in nomal opeation which is one of the impotant featues of on-line UPSs especially when the utility system is weak. To ovecome this dawback, thee is no choice othe than using the convete in DF mode of opeation. Nonetheless, the disadvantage of woking in DF mode is educed DC bus utilization which by itself inceases the stess of the switches, switching loss and output voltage THD. To maintain the fequency independency of the convete while minimizing the weaknesses of DF mode it is suggested to find an appopiate opeating point consideing specifications of the convete such as powe ating, input souce and dc bus voltage levels and the line inductance. The pincipal condition of woking in DF mode is that the sum of ectifie and invete modulation indices should be equal to o less than one. As mentioned ealie, conventionally half of the total modulation index is dedicated to the ectifie stage and the othe half to the invete stage. Howeve, this allocation of the dc bus voltage is not optimal. The optimized pecentage of dc bus voltage fo ectifie and invete stages, i.e. optimal opeating point of the convete, can be obtained by taking the convete specifications into account as follows: The input active and eactive powe of the convete is defined by (5). VV s c Pin = sinδ X (5) Vs Qin ( Vc cos δ Vs ) = X whee V s and V c ae espectively the ms values of netwok and ectifie input teminal voltages, δ is the phase diffeence between them and X is the input eactance. Assuming a constant dc bus voltage level, the ectifie acside voltage is decided by (6). V = M V sin( ω t δ) (6) c dc s 410
Disegading convete loss and assuming a unity powe facto means: Pin = Pout (7) Qin = 0 Applying (7) to (5) and (6), two conditions ae deived fo convete opeating point stated by (8). Vs M cosδ = Vdc (8) XL P in out M sinδ = VV s dc Fom (8), the maximum modulation index of the ectifie stage could be obtained vesus design paametes of the convete as : V X P M V V s out = ( ) (9) dc s Consideing nominal V s and I s as the base values, the peunit value of P will be as (10). Substituting pe-unit values in (9), (11) would be the pe-unit equation of the system fo nomal opeation. M,Max is also deived fo maximum input cuent. φ 0 in s s cosφ = in, pu s, pu s, pu P = VI P = V I (10) ( XL,, ) in puis pu M = Vdc, pu (11) X, pu M Max, = Vdc, pu As shown by (11), while woking unde nominal conditions, the maximum amount of M is invesely popotional to dc bus voltage level which is at least 1.41V s to popely contol the ectifie and is diectly popotional to the inseted eactance. Fig. 10 illustates the elationship between M vesus dc bus voltage fo diffeent values of X while woking unde nominal conditions (I s,pu =1). The souce fequency is assumed to be 60Hz. V. PROPOSED STRATEGY FOR BATTERY CHARGING In the pevious section, the optimal opeating point was discussed. It is woth to notice that the maximum value of M was obtained only based on the load maximum demanded powe. Howeve, when the battey is also getting chaged, this value of modulation index will be unable to povide both load powe and battey chaging powe. To eliminate the undesiable effect of loweing the ectifie modulation index on maximum input powe while the battey is getting chaged, a paticula stategy is poposed. Fig. 10. M, Max vesus Vdc (pu) fo diffeent input eactance values Afte fault emoval, when the battey is not supplying the load anymoe, it should get chaged as soon as possible to be pepaed fo supplying the load immediately in the next pobable fault. Hence, duing the battey chaging peiod, the opeating mode would be bette to change fom DF to EF mode so that the ectifie modulation index could incease up to one and the maximum possible powe could be tansfomed to the battey and the load at the same time. This would incease the possible absobed powe fom the netwok by (1). P EF M (0-1) 1 M = X X P Vdc( 1-10, pu) Max, PDF DF MMax, MMax, (1) Afte the battey is chaged, the opeating point would again etun to its nomal state in ode to maintain fequency isolation. VI. SIMULATION RESULTS Fo simulating the poposed system, it is decided to decease the value of dc bus voltage level by inceasing the invete stage modulation index. This will educe the maximum output powe of the invete since the value of input powe is deceased. Howeve, since poviding a specified voltage and not constant nominal powe is the fist pioity of UPS systems, this limitation is justified. This means that the dc bus voltage level is educed hee at the expense of maximum output powe eduction. It is woth to notice that highe invete modulation index deceases output voltage THD and lowe dc bus voltage educes the switching loss. To demonstate the effectiveness of the poposed method, a typical system is designed accoding to netwok specifications and load equiements tabulated in table I. TABLE I. NETWORK SPECIFICATIONS AND LOAD REQUIREMENTS Paametes Value Paametes Value V s 00 Vp-p V o 450 Vp-p f s 58-6 Hz f o 60 Hz P load 1.5 kw PF 1 411
V dc and L in ae the two degees of feedom in obtaining the convete paametes and the optimal opeating point. It should also be noted that these values ae also the decisive factos fo detemining maximum output voltage level and input cuent THD. Optimal values ae decided in a cyclic pocedue fo satisfying all the citeions. The final calculated values of the nomal opeating point, dc bus voltage level and input inductance which ae used hee ae tabulated in Table II. If the conventional method wee used, the level of dc bus voltage would be 450 V fo this convete. But accoding to Table II, this value is 350v fo the novel method. This means that the dc bus voltage level is educed by.%. TABLE II. OPTIMALLY CALCULATED DESIGN PARAMETERS Paametes Value Paametes Value V dc 350 V L in 6 mh M, Max 0.35 M i, Max 0.65 -Cuent (A) Cuent (A) -10, 0, 10 Nomal input Simulation is caied out when the system is functioning in two modes of DF and EF. In both modes of opeation, the pefomance of the convete is checked when the input souce expeiences voltage sag fo linea and non-linea loads. Switching fequency and dc bus capacito ae 5 khz and 1880uF, espectively. A. DF Mode of Opeation In nomal opeation, when the battey is chaged, the convete woks in DF mode(f o =60Hz) in the fomely obtained opeating point. Fig. 11 and 1 show the system pefomance unde 0% input voltage sag when supplying linea and nonlinea loads of the same powe. The input cuent THDs fo linea and non-linea loads ae 3.43% and 3.53% espectively. The sinusoidal input cuent, unity powe facto, stabilized dc bus voltage and the constant injected powe to the system ae the desiable chaacteistics the convete possesses. 50, 360 B. EF Mode of opeation EF mode of opeation is simulated fo the case when 600 W is dawn fom the dc bus fo battey chaging. The value of invete modulation index and hence output voltage has not changed. This veifies the ability of the convete to absob moe powe than nomal condition which is esulted by inceasing the ectifie modulation index value. The same happens when a conventional on-line UPS is chaging the battey. It should be noticed that the nomal opeating point is obtained based on output load powe but the convete should be designed to povide the maximum powe demanded simultaneously by the battey and the load. P(W), Q (va) -50, 0, 100 Fig. 11. DF mode of opeation, linea load a- Input souce voltages and cuents b- Load cuents d- Input active/eactive powe The system pefomance could be obseved duing input souce voltage sag in Fig. 13 and 14 fo two instances of linea and non-linea loads. Compaed to DF opeation, the load cuent has not changed since the invete modulation index is fixed but the input cuent has isen to supply the battey powe. The input cuent THDs fo linea and non-linea loads ae 1.93% and.36% espectively. Opeation of the convete when the input is expeiencing voltage sag, is distinguished fom the nomal mode via dotted line in all the esult figues. It can be seen that the system has a fast dynamic esponse whethe woking in DF o EF modes of opeation unde both linea and non-linea load conditions. 41
Nomal input Nomal input -Cuent (A) Cuent (A) -0, 0, 0 50, 360 P(W), Q (va) -50, 0, 100 -Cuent (A) Cuent (A) -10, 0, 10 P(W), Q (va) -50, 0, 1850 50, 360 Fig. 1. DF mode of opeation, non-linea load a- Input souce voltages and cuents b- Load cuents d- Input active/eactive powe VII. CONCLUSION A new two-leg type educed-switch-count topology was intoduced and a modulation scheme was elaboated fo it. A new method of detemining optimal opeating point was developed. This method is also applicable to thee-phase convetes of the same type. Fig. 13. EF mode of opeation, linea load a- Input souce voltages and cuents b- Load cuents d- Input active/eactive powe Oveall, the poposed convete and the suggested opeating point along with the poposed stategy fo the battey chaging enjoys seveal advantages ove its thee-phase countepat such as being suitable fo low powe/voltage applications, enhanced dc bus utilization, educed switching loss, impoved output voltage THD, expedited battey chaging ate, etc. 413
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