74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 00-mA Typical Latch-Up Immunity at 2 C description This device coists of bus traceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed tramission of data directly from the data bus or from the internal storage registers. Enable GAB and are provided to control the traceiver functio. SAB and SBA control pi are provided to select whether real-time or stored data is traferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the traition between stored and real-time data. A low input level selects real-time data, and a high selects stored data. Figure illustrates the four fundamental bus-management functio that can be performed with the octal bus traceivers and registers. GAB A A2 A3 A4 A A6 A7 A8 DW PACKAGE (TOP VIEW) 2 3 4 6 7 8 9 0 2 3 4 28 27 26 2 24 23 22 2 20 9 8 7 6 CAB SAB B B2 B3 B4 V CC V CC B B6 B7 B8 CBA SBA Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high traitio at the appropriate clock pi (CAB or CBA), regardless of the select or enable control pi. When SAB and SBA are in the real-time trafer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remai at its last state. The 74ACT62 is characterized for operation from 40 C to 8 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Itruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Itruments Incorporated POST OFFICE BOX 6303 DALLAS, TEXAS 726
74ACT62 BUS A BUS B BUS A BUS B GAB CAB CBA SAB SBA GAB CAB CBA SAB SBA L L X X X L H H X X L X REAL-TIME TRANSFER BUS B TO BUS A REAL-TIME TRANSFER BUS A TO BUS B BUS A BUS B BUS A BUS B GAB CAB CBA SAB SBA GAB CAB CBA SAB SBA X H X X X L L H or L H or L X H L X X X X L H X X STORAGE FROM A AND/OR B TRANSFER STORED DATA TO A AND/OR B Figure. Bus Trafer Diagram 2 POST OFFICE BOX 6303 DALLAS, TEXAS 726
INPUTS FUNCTION TABLE DATA I/O GAB CAB CBA SAB SBA A A8 B B8 L H H or L H or L X X L H X X 74ACT62 OPERATION OR FUNCTION Isolation Store A and B data X H H or L X X Upecified Store A, hold B H H X X Store A in both registers L X H or L X X Upecified Hold A, store B L L X X Store B in both registers L L X X X L L L X H or L X H H H X X L X H H H or L X H X Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and H L H or L H or L H H stored B data to A bus The data-output functio may be enabled or disabled by various signals at the GAB or inputs. Data-input functio are always enabled, i.e., data at the bus terminals is stored on every low-to-high traition on the clock inputs. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. logic symbol 4 CBA SBA CAB SAB A A2 6 28 27 2 3 EN [BA] EN2 [AB] C4 G C6 G7 6D 7 7 4D 2 26 2 B B2 A3 4 24 B3 A4 23 B4 A 0 20 B A6 9 B6 A7 2 8 B7 3 A8 7 B8 This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. POST OFFICE BOX 6303 DALLAS, TEXAS 726 3
74ACT62 logic diagram (positive logic) 4 GAB CBA SBA CAB SAB 6 28 27 One of Eight Channels D C A 2 D C 26 B To Seven Other Channels absolute maximum rating over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC............................................................... 0. V to 7 V voltage range, V I (see Note )........................................... 0. V to V CC + 0. V voltage range, V O (see Note )........................................ 0. V to V CC + 0. V clamp current, I IK (V I < 0 or V I > V CC )................................................ ±20 ma clamp current, I OK (V O < 0 or V O > V CC )............................................ ±0 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±0 ma Continuous current through V CC or.................................................. ±200 ma Maximum power dissipation at T A = C (in still air) (see Note 2)................................7 W Storage temperature range, T stg................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 0 C and a board trace length of 70 mils. recommended operating conditio (see Note 3) MIN MAX UNIT VCC Supply voltage 4.. V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI voltage CC V VO voltage CC V IOH High-level output current 24 ma IOL Low-level output current 24 ma t/ V traition rise or fall rate 0 0 /V TA Operating free-air temperature 40 8 C NOTE 3: Unused inputs must be held high or low to prevent them from floating. 4 POST OFFICE BOX 6303 DALLAS, TEXAS 726
74ACT62 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VOH VOL PARAMETER TEST CONDITIONS VCC IOH = 0 A IOH = 24 ma TA = 2 C MIN TYP MAX 4. V 4.4 4.4. V.4.4 MIN MAX UNIT 4. V 3.94 3.8 V. V 4.94 4.8 IOH = 7 ma. V 3.8 IOL =0A IOL =24mA 4. V 0. 0.. V 0. 0. 4. V 0.36 0.44 V. V 0.36 0.44 IOL = 7 ma. V.6 IOZ A or B ports VO = VCC or. V ±0. ± A II GAB or VI = VCC or. V ±0. ± A ICC VI = VCC or, IO = 0. V 8 80 A ICC One input at 3.4 V, Other inputs at or VCC. V 0.9 ma Ci GAB or VI = VCC or V 4. pf Co A or B ports VO = VCC or V 2 pf Not more than one output should be tested at a time, and the duration of the test should not exceed 0 ms. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than or VCC. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER TA = 2 C MIN MAX UNIT fclock Clock frequency 0 0 0 0 MHz tw Pulse duration, CAB or CBA high or low 4.8 4.8 tsu Setup time, A before CLK or B before CBA 4 4 th Hold time, A after CAB or B after CBA 2. 2. MIN MAX POST OFFICE BOX 6303 DALLAS, TEXAS 726
74ACT62 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) PARAMETER FROM TO TA = 2 C (INPUT) (OUTPUT) MIN TYP MAX MIN MAX UNIT fmax 0 0 MHz AorB BorA 3.8 7 9.9 3.8. 3.4 6.7 0.7 3.4.6.4 8.4.8.4 3. CBA or CAB AorB 6. 9.4 3. 6. 4.4 SBA or SAB 2.8 6.2 0. 2.8 AorB with A or B high. 8.7 2.. 3.3 SBA or SAB 4.9 7.8 4.9 2.2 AorB with A or B low 3.9 7..6 3.9 2.6 tpzh 3.3 7.2.4 3.3 2.6 A tpzl 4. 7.8 2.6 4. 3.8 tphz.2 7.2 9.3.2 9.9 A tplz 4.8 6.7 8.6 4.8 9.3 tpzh. 9. 3.4..2 GAB B tpzl.8 9.7 4.2.8 6. tphz 3.4 6.8 9.7 3.4 0.3 GAB B tplz 3. 6 8.8 3. 9.3 These parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, V CC = V, T A = 2 C Cpd PARAMETER TEST CONDITIONS TYP UNIT s enabled 9 Power dissipation capacitance per traceiver CL =0pF pf, f=mhz pf s disabled 4 6 POST OFFICE BOX 6303 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION 74ACT62 From Under Test CL = 0 pf (see Note A) 00 Ω 00 Ω S 2 VCC Open TEST / tplz/tpzl tphz/tpzh S Open 2 VCC LOAD CIRCUIT tw. V. V Timing Data tsu. V. V th. V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS In-Phase Out-of-Phase. V. V VOH VOL VOH VOL Control (low-level enabling) Waveform S at 2 VCC (see Note B) Waveform 2 S at (see Note B) tpzl tpzh. V tplz tphz. V 20% VCC 80% VCC VCC VOL VOH VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr = 3, tf = 3. D. The outputs are measured one at a time with one input traition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 6303 DALLAS, TEXAS 726 7
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