Lecture (07) BJT Amplifiers 4 JFET (1) By: r. Ahmed Elhafee 1 Capacitively Coupled Multistage Amplifier we will use the two stage capacitively coupled amplifier in Figure The output of the first stage capacitively coupled to the input of the second stage. 2
Capacitive coupling prevents the dc bias of one stage from affecting that of the other but allows the ac signal to pass without attenuation XC==0 3 Loading Effects the total input resistance of the second stage presents an ac load to the first stage. the effective ac collector resistance of Q1 is the total of all these resistances in parallel (R3, R5, R6, and Rin(base2)) 4
The ac collector resistance of the first stage is Therefore, the base to collector voltage gain of the first stage is Voltage ain of the econd tage; The second stage has no load resistor, so the ac collector resistance is R7, and the gain is 5 Overall Voltage ain If an input signal of 100uv, then output voltage is = (100 mv)(13,495) =1.35 V 6
C Voltages in the Capacitively Coupled Multistage Amplifier ince both stages are identical, the dc voltages for Q1 and Q2 are the same. β C R4 >> R2, β C R8 >> R6 7 irect Coupled Multistage Amplifiers no coupling or bypass capacitors in this circuit. The dc collector voltage of the first stage provides the base bias voltage for the second stage. Because of the direct coupling, this type of amplifier has a better low frequency response (irect coupled amplifiers can be used to amplify low frequencies all the way down to dc (0 Hz) ) than the capacitively coupled. The increased reactance of capacitors at lower frequencies produces gain reduction in capacitively coupled amplifiers. 8
differential amplifier (diff amp) 1. when both inputs are grounded (0 V), the emitters are at 0.7V. It is assumed that the transistors are identically matched by careful process control during manufacturing so that their dc emitter currents are the same when there is no input signal. 9 ince both collector currents and both collector resistors are equal 10
2 Next, input 2 is left grounded, and a positive bias voltage is applied to input 1, The positive voltage on the base of Q1 increases IC1 and raises the emitter voltage to This action reduces the forward bias (VBE) of Q2 because its base is held at 0 V (ground), IC2 decrease 11 increase in IC1 causes a decrease in VC1, and the decrease in IC2 causes an increase in VC2, 12
3 Finally, input 1 is grounded and a positive bias voltage is applied to input 2. Applied V B2, increases IC2, decrease in VC2, V E2 voltage is raised. reduces the forward bias of Q1, decrease in IC1 causes VC1 to increase 13 Modes of ignal Operation ingle Ended ifferential Input: one input is grounded and the signal voltage is applied only to the other input, inverted, amplified signal voltage appears at output 1 as shown a signal voltage appears in phase at the emitter of Q1 14
Q1 is common, emitter signal becomes an input to Q2, which functions as a common base amplifier at Q2 output 2; amplified noninverted signal. 15 In the case where the signal is applied to input 2 with input 1 grounded, an inverted, amplified signal voltage appears at output 2, noninverted, amplified signal appears at output 1. 16
ouble Ended ifferential Inputs: two opposite polarity (out of phase) signals are applied to the inputs 17 18
Common Mode Inputs: two signal voltages of the same phase, frequency, and amplitude are applied to the two inputs 19 20
This action is called common mode rejection. Common mode rejection means that this unwanted signal will not appear on the outputs and distort the desired signal. Common mode signals (noise) generally are the result of the pick up of radiated energy on the input lines from adjacent lines, the 50 Hz power line, or other sources. 21 Common Mode Rejection Ratio esired signals appear on only one input or with opposite polarities on both input lines. These desired signals are amplified and appear on the outputs as previously discussed. Unwanted signals (noise) appearing with the same polarity on both input lines are essentially cancelled by the diff amp and do not appear on the outputs. The measure of an amplifier s ability to reject common mode signals is a parameter called the CMRR (commonmode rejection ratio). 22
Ideally, a diff amp provides a very high gain for desired signals (single ended or differential) and zero gain for common mode signals, practically is a very small value 23 Example 02 24
25 JFET Basic tructure Figure shows the basic structure of an n channel JFET (junction field effect transistor). Wire leads are connected to each end of the n channel; the drain is at the upper end, and the source is at the lower end. Two p type regions are diffused in the n type material to form a channel, and both p type regions are connected to the gate lead. For simplicity, the gate lead is shown connected to only one of the p regions. A p channel JFET is shown in Figure 26
Basic Operation To illustrate the operation of a JFET, Figure shows dc bias voltages applied to an n channel device. V provides a drain to source voltage and supplies current from drain to source. V sets the reverse bias voltage between the gate and the source, as shown. 27 a negative gate voltage produces a depletion region along the pn junction, which extends into the n channel and thus increases its resistance by restricting the channel width. The channel width and thus the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current, I. 28
The white areas represent the depletion region created by the reverse bias. It is wider toward the drain end of the channel because the reversebias voltage between the gate and the drain is greater than that between the gate and the source 29 30
JFET ymbols The schematic symbols for both n channel and p channel JFETs are shown in Figure 31 FET characteristic and perameters The JFET operates as a voltage controlled, constant current device. (V = 0 V), gate to the source both are grounded. As V (and thus V) is increased from 0 V, I will increase proportionally, 32
In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect This is called the ohmic region because V and I are related by Ohm s law 33 At point B, enters the active region where I becomes essentially constant. As V increases from point B to point C, the reverse bias voltage from gate to drain (V) produces a depletion region large enough to offset the increase in V, thus keeping I relatively constant. 34
Pinch Off Voltage For V =0 V, the value of V at which I becomes essentially constant, point B on the is the pinch off voltage, VP. For a given JFET, VP has a fixed value. a continued increase in V above the pinchoff voltage produces an almost constant drain current. This value of drain current is I (rain to ource current with gate horted) and is always specified on JFET datasheets. 35 I is the maximum drain current that a specific JFET can produce regardless of the external circuit, and it is always specified for the condition, V 0 V. 36
Breakdown breakdown occurs at point C when I increase very rapidly with any further increase in V. Breakdown can result in irreversible damage to the device, so JFETs are always operated below breakdown and within the active region (constant current) 37 38
Thanks,.. ee you next week (IA), 39