Signal integrity means clean

CHIPS & CIRCUITS As you move into the deep sub-micron realm, you need new tools and techniques that will detect and remedy signal interference. Dr. Lynne Green, HyperLynx Division, Pads Software Inc The Effects of Signal Integrity in Sub-Micron Chip Design Signal integrity means clean data; put another way, a lack of signal integrity means corrupted data. In any high-speed circuit design, signal integrity is a major concern. Signal integrity failures introduce free transitions, leading to either bad data being captured into a latch or a bad clock edge causing data to be captured at the wrong time. In the early days, signal integrity was primarily an issue in RF board design. Today, as circuit design continues to migrate to deep sub-micron IC scales and faster switching speeds, maintaining signal integrity is an even greater challenge. Designers must locate sources of possible interference early in the design cycle and eliminate them before they cause problems. This will become easier as design tools and techniques adapt to meet the signal integrity challenge. The origins of signal integrity problems lie in the circuit interconnections (wires, substrates, and wells). A wire serves not only as a conductor of electrons, but also as a resistor (at low frequencies), a capacitor (at midrange frequencies), an inductor (at high frequencies), or an antenna (at very high frequencies). All of these characteristics can adversely affect signal integrity. One way of estimating which of these effects is dominant is to look at the wire s impedance at various frequencies. A package interconnect might have 1 0 Volts GND Quiescent Signal Figure 1. The quiescent line must stay below the logic low level or above the logic high level, or data or clocking errors may occur. 5 Ω + 50 pf + 10 nh. At a frequency of 100 MHz, the corresponding impedances are [5, -j32, +j6]. All three terms are comparable in magnitude. As a general rule, the larger the series (R and L) terms and the smaller the shunt (C) term, the more significant each term becomes. For digital switching edges, the frequency used in this calculation is typically 10/tr, where tr is the signal rise time, although 3/tr can be sufficient for some needs. Time VH Quiescent Lines Are Not Always Quiet Figure 1 shows an example of poor signal integrity. In the simulated switching waveforms, the quiescent line shouldn t cross the logic low level line (the dashed line) or the logic high level line (the dotted line). Because the quiescent line does cross the logic low-level line, data errors or clocking errors may occur. It is acceptable for Vdd and GND to cross those logic levels as long as they are connected only to the output-drive FETs. Another signal integrity problem is a signal that violates a voltage constraint. In the simulated switching waveforms, both the quiescent and switching lines ring. The ringing frequency is set by the load capacitance and the package inductance (ω=1/ (LC)). The 10

switching waveform exhibits both overshoot and undershoot, and the quiescent waveform exhibits ringing. An I/O cell must be designed so that the quiescent waveform does not cross VOL or VOH during simultaneous switching output (SSO) operation, where VOH and VOL are the output-high and output-low voltages for the I/O interface specification (VOH 2.4 V and VOL 0.4 V for TTL). As ICs scale below 0.5 microns, maintaining signal integrity becomes more challenging, primarily because of faster rise times and the underlying physics of silicon design. Timing in particular becomes more sensitive to wiring parasitics as chip designs move into the very deep sub-micron domain (0.25 microns and below). Also, ground bounce increases because of faster signal rise times and package parasitics. The Primary Factors There are five primary factors that have a profound impact on signal integrity in silicon design, particularly sub-micron design: resistance, capacitance, inductance, crosstalk, and substrate coupling. In any silicon design, resistance is caused by the interaction of the current-carrying electrons with the atoms and crystalline grains in the metal. As features shrink below 0.5 microns, surface effects may cause the resistance of a piece of metal to decrease more slowly than the cross-sectional area, resulting in a loss of signal integrity. Foundries are addressing this problem by incorporating new metals that minimize resistance. Capacitance results from the closeness of structures with independent voltages. A reduction in design rules has two effects. First, as wires become smaller, capacitance becomes dominated by the wire-spacing dimensions. Second, as the spacing between wires decreases, capacitance increases. In the domain of deep sub-micron design, wiring capacitance is dominated by fringing and lateral terms instead of area, so traditional capacitance calculators can be off by a factor of two or more (high or low, depending on the net). As silicon foundries move to five and six layers of metal, capacitance calculations become more complex. For example, a piece of metal on layer 4 may be completely shielded from the substrate by intervening wiring. Thus it s no longer sufficient to calculate capacitances to the substrate. Instead, capacitances are dominated by internodal effects, so the calculations must be adjusted accordingly. Moving into the 3D World Today, chip designers must use 3D field solvers to extract those capacitances. In the future, foundries need to provide internodal capacitances, including fringing as well as area effects. The SIPPs model, similar to the BSIM model for transistors, provides a way for the foundries to communicate modeling of interconnects to users. Inductance remains a concern primarily at the package and board levels. It is dictated by both the size of the wire and the distance to the return path (usually another wire nearby or, in the case of silicon, a substrate/ground plane). As ICs scale below 0.5 microns, inductance can become significant. Inductances of even a few nanohenries on-chip can be a problem if they are in an I/O pad, where high switching currents in the power rails can produce Vdd and ground noise that can be coupled into quiescent logic. When two wires run in parallel, there is also a mutual inductance that can couple noise onto a quiescent line. To calculate inductance, the following approximation can be used: L = (µ 0 )/(2π) ln(8h/w + W/4H) where H is the height of the metal above the silicon and W is the metal strip width. However, this approximation is not very accurate for deep sub-micron design, where H is larger than W. Crosstalk on Chips Crosstalk is another signal integrity problem that grows with both increasing chip clock speeds and decreasing design rules. Crosstalk isn t a major issue below 10 MHz on boards and 100 MHz on chips, but above 100 MHz on boards and 11

CHIPS & CIRCUITS CONTINUED Simultaneously Switched Outputs 1,000 MHz on chips, it is known to be significant. For frequencies in between, crosstalk is a definite risk, especially at the I/O interface, where there are board-level as well as chip-level effects. As sizes scale down, though, these rules of thumb lose their validity. Crosstalk is the result of capacitive and inductive coupling between adjacent wires, which causes each wire to act as an antenna. Crosstalk is typically observed as a fast dv/dt or di/dt in one wire, causing a second wire to respond. At 0.5 microns, this can be adequately modeled as pure Unswitched Outputs Figure 2. To ease simulation, one cell represents all of the simultaneously switching outputs and the remaining cells represent the unswitched outputs. capacitive coupling (displacement current). However, as dimensions shrink to 0.18 microns, inductive coupling becomes significant as well. Unfortunately, most IC-level 3D field extractors are not being used to extract inductance, so designers won t realize there is a problem until a design fails. Therefore, the best strategy for dealing with crosstalk is to spot the failure using a 3D extractor and then to perform simulation. Substrate coupling also generates signal integrity problems that grow worse as sizes scale down. Because the substrate and wells have a finite resistivity, any current flow will cause a voltage drop. A MOSFET s threshold (turn-on) voltage depends on the effective voltage of the substrate (or well) immediately below the gate region, which means that any substrate current can shift not only the threshold of the MOSFET, but also the threshold of the logic gate or clock circuitry. As horizontal dimensions are scaled down, the vertical dimensions are often scaled down as well, increasing the resistance of the substrate and well layers. Historically, chip and multichip designers have used two approaches to solve the problems of signal integrity. The RF solution has focused on transmission lines, using impedance matching at the package boundaries. The digital (broadband) solution has emphasized care in package selection, controlling the number of simultaneously switching outputs and/or switching speeds and using decoupling capacitors between Vdd and GND at the external package pins. As designers address the problem of signal integrity in deep submicron designs, they have found that those solutions are no longer adequate. For example, limiting di/dt, although greatly improving ground bounce and crosstalk, limits the clock speed. New approaches must be adapted for deep submicron design. For instance, the problem of increasing substrate resistance can be addressed by 12

using silicon-on-insulator (SOI) technology, a proven technique in microwave IC design. Unfortunately, IC designers rarely have the option to change the foundry process. Sub-Micron Signal Integrity Solutions So what are deep sub-micron designers to do? The signal integrity problem can be addressed in three ways: circuit design, placement and routing, and simulation. In circuit design, designers have many choices and can control signal integrity by designating the number of simultaneous switching outputs, the maximum di/dt and dv/dt of each cell, and so on. Designers may also choose to use differential signals for high-fanout blocks such as clock drivers. The most common example is positive- ECL signals for clocks, or full-swing differential. Both can be used onchip as well as off-chip. In placement and routing, the choices are more limited. Rule-driven routers have only recently become available for printed circuit boards, and although there are some rule-driven routers for ICs, none are driven by user-defined rules or support signal integrity analysis. The place-and-route tools should incorporate full parasitic extraction (preferably near 3D) to allow accurate prediction of slew rates (since it s slew rates that drive signal integrity) as well as delays. The ultimate router would not only have accurate parasitic extraction, it would also incorporate a signal integrity tool that would rip up and reroute if signal integrity fell below the desired threshold. The third and most obvious solution is to simulate circuits with care. If there is no accurate parasitic extractor, then it s up to the designers to estimate the correction factors. In one study we conducted at Duet Technologies, we found that 3D capacitances (actually, 2D with some 3D effects) were about twice the value obtained using area-tosubstrate-only effects. Therefore, during simulation all capacitances should be modeled as internodal rather than as capacitances to ground. This allows observation of crosstalk effects on quiescent nodes, and also gives more accurate delay and slew rate predictions. Simulation must be done on the circuit in its package environment so that the simulation results will more closely correspond to the results of tests after the silicon comes back from the foundry. This also pushes the final validation of the signal integrity from IC designers to the IC users. As clock speeds increase, this becomes one of the critical validation or verification steps. Simulation Shortcuts Simulation has another problem too. It is time consuming to run SPICE on an SSO circuit containing a dozen or more I/O cells, particularly when each circuit contains on the order of 100 transistors including drive, logic, and ESD devices. At Duet, we designed a circuit to reduce the SSO test structure for SPICE simulation significantly (Figure 2). The first cell represents the N simultaneously switching outputs. The current of all N of these flows through the Vdd and GND package parasitics. The cell has the same load for each SSO. N is an input parameter, allowing the tradeoff between rail bounce and number of SSOs to be quickly checked. The remaining cells are not switching. There are four static cells supplied with their Vdd and GND signals from the same chip-port voltage, so they see all of the bounce on both rails. The cells provide monitoring of PADPIN high and low, and of Y high and low, allowing detection of signal integrity problems due to rail coupling. The waveforms produced by the circuit have their peak and period in close agreement with corresponding lab measurements, often within 5 percent. High-frequency effects due to Vdd and GND inductance on the chip are not modeled in our test circuit. This circuit allows us to simulate the effects of SSO in a few minutes. This is much faster than running SPICE on the entire N switching cells, so we can run SSO simulations over 16 corners or under various design conditions in a single day. 13

CHIPS & CIRCUITS CONTINUED Shrinking Devices, Expanding Challenges As IC dimensions continue to scale down, maintaining signal integrity becomes an ever-increasing challenge for circuit designers. Since signal integrity problems often appear as intermittent errors, it becomes more important to fix problems before silicon is fabricated. Designers will be required to spend more time on issues such as simultaneous switching control, simulation, and packaging before chip fabrication. To further complicate matters, scaling increases resistance and inductance without significantly decreasing capacitance, so that layout to minimize wire length will become even more critical. At the same time, new routing rules to minimize quiet nets in parallel with noisy nets will have to be added to physical design tools to overcome signal integrity problems in deep sub-micron design. Guaranteeing that a design meets signal integrity requirements will require routers that incorporate signal integrity verification. As designers continue to shrink circuits down to even deeper submicron levels, simulation will no longer be sufficient to validate signal integrity; a silicon prototype will be required. To aid designers in planning circuits with acceptable signal integrity, signal integrity data must appear on data sheets, and the package information must incorporate signal Measure Reality to Enhance Simulation hen validating the accuracy of a simulation approach, you must often make real-world measurements in the lab. You can make these measurements with an HP 81100 family pulse generator, two DC power supplies (HP 3610A), a digital multimeter for DC testing (HP 34401A), an HP Infinium oscilloscope to monitor the output, an IEEE 488 bus, and a PC. Since rise times are on the order of 1 to 2 nanoseconds, it is particularly critical to have impedancematched signal and scope ports. The components must be laid out to minimize lead length, and high-speed grounding layout rules must also be used. W integrity characteristics in order to be useful to the user community. Although we have a long way to go before the EDA industry develops the design tools, signal integrity verification strategies, and databook information formats required to address the challenges of signal integrity in deep sub-micron design, significant progress has been made. The proliferation of parasitic extractors (both 2D and With up to 1.5-GHz bandwidth and up to 8-Gsa/s sample rate, the HP Infinium provides the performance needed to make these measurements. It also has an easy-touse interface with an analog-like front end that has simple controls for basic operations and the familiar Windows 98-based graphical user interface to access the advanced features. This ease of use allows you to quickly make complex measurements without having to ponder a cluttered front panel or waste valuable time reading a manual, even if you don t use the Infinium on a regular basis. For more information, check 2 on the reply card, or visit http://www.hp.com/info/insight3. 3D) is an indication of the willingness of EDA vendors to respond to industry needs. Over the next two to three years, the industry should see interesting developments in the evolution of cell design, place-and-route tools, and verification tools. The secret to maintaining signal integrity is to continue working on better design tools and techniques. 14