GC5325 Wideband Digital Predistortion Transmit IC Solution. David Brubaker Product Line Manager Radio Products February 2009

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Transcription:

GC5325 Wideband Digital Predistortion Transmit IC Solution David Brubaker Product Line Manager Radio Products February 2009

Broadband Wireless Standards drive BTS design complexity Increased subscriber demand for wireless service within limited/licensed RF spectrum has forced the industry to adopt wideband, complex, spectrally efficient modulation schemes to increase voice and data capacity over cellular networks. 3G and OFDM-based signals (WiMAX, LTE, UMB) have tougher Error Vector (EVM) and larger Peak-to-Average (PAR) requirements. Such signals are more sensitive to intermodulation distortion (IMD) and as result multi-carrier power amplifiers (MCPA) have to work far from saturation, where they are less efficient. Lower efficiency power amplifiers (PAs) have traditionally represented 30% of the overall BTS system cost. As a result, the MCPA has challenging cost, performance, and efficiency tradeoffs which BTS designers must optimize in order to meet spectral mask requirements.

The Solution Digital Pre-Distortion Linearization with CFR Digital Pre-distortion (DPD) performs a mathematical inversion of the non-linear transfer function of the Power Amplifier (PA) to cancel out IMD products generation. This is accomplished by using real-time feedback to monitor the PA output and make corrections. Digital Pre-Distortion allows a PA to be operated at higher power with minimal IMD increases and thus greater efficiency. Increased efficiency relaxes multi-carrier power amplifier (PA) design specifications and thus reduces PA Bill of Material (BOM) costs. Crest factor reduction (CFR) can further increase the efficiency of the PA by reducing the peak-toaverage ratio (PAR) of the transmitted signal. Input Pre- Distorter PA Output Output Power Linear output extended by DPD GC5325 CFR-DPD Input Power

GC5325 Wideband Digital Predistortion Transmit IC Solution Integrated functional transmitter blocks include: Crest factor reduction (CFR) Digital pre-distortion (DPD) Flexible DSP algorithm supports existing and emerging wireless standards Integrated CFR and DPD increase PA efficiencies Integrated DPD reduces adjacent channel leakage ratio (ACLR) 20MHz Bandwidth for 5 th order correction Integrated IQ imbalance correction Fully automated channel equalizer Extremely fast DPD convergence times Robust convergence algorithm High Integration - reduces design complexity, power consumption, development time, implementation size and bill-of-material (BOM) costs High Performance: Integrated DPD reduces adjacent channel leakage ratio (ACLR) by 20 db or more Increases PA efficiencies to 25 percent or more for Class AB PAs and greater than 40 percent for Doherty PAs Flexibility - DPD architecture incorporates a TI DSP to run the fully adaptive linearization algorithm Complete Solution - complete signal chain solution reduces time-to-market and design risks Robust - Convergence algorithm allows dynamic carrier allocation, without disrupting cellular service UART C6727 DSP EMIF SDRAM/Flash 3GPP (W-CDMA, TD-SCDMA) Base Stations 3GPP2 (CDMA2000) Base Stations WiMAX, WiBRO, LTE (OFDMA) Base Stations Multicarrier Power Amplifiers (MCPAs) Two-Channel Transmit Diversity Applications Military Radio Transmitters CPRI/ OBSAI Host and Baseband Processor BB I/Q Data EMIF GC5325 CFR-DPD I/Q DAC5682z DAC ADC ADS6149 I Q SPI RF Card I/Q Modulator TRF3703 THS9000 Mixer HPA

Supported Signal Characteristics: Slide 1 Spectral Composite Signal Bandwidth < 20 MHz Individual Carrier Bandwidth > 1 MHz Occupied Bandwidth > 20% Example: CDMA with 20 MHz span must have >= 4 carriers Example: CDMA with 10 MHz span OK with 2 carriers Composite BW Carrier # 1 2 3 N (# Carriers)*(Carrier BW) Occupied BW = Composite BW Carrier BW RF Frequency

Supported Signal Characteristics: Slide 2 Time TDD or FDD Static Configurations Only no frequency hopping New configurations require stopping DPD and reloading GC5325 configuration RF Frequency Bands for EVM Hardware Today: 1600-3500 MHz 1Q09: 700-1400 MHz

GC5325 Functional Block Diagram GC5325 RESETB SYNCD (LVDS) SYNC 3 SYNC OUT INT UPDATA 16 TCK UPADDR OEB RDB WRB CEB TRSTB TDO 10 TDI 4 TMS MPU Interface JTAG BB BBFR Input Demux CFR Fractional Resampler Circular Limiter BB PLL DPD PLL BBCLK DPDCLK (LVDS) FB (LVDS) MFIO 18 34 (ADC input or MAG output) ADC Interface Real to Complex (or bypass) Feedback Equalizer Feedback NL correction TX 38 DAC Interface Bulk Interpolation + Mixer Transmit Equalizer DPD Capture Buffers

GC5325 Transmit Solution Architecture C6727 EMIF UART DSP SDRAM/Flash SPI EMIF RF Card CPRI/ OBSAI Host, Baseband Processor, DUC Composite I/Q Data GC5325 CFR-DPD I/Q DAC5682z DAC ADC I Q I/Q Modulator TRF3703 HPA ADS6B149 THS9000 Mixer

GC5325 Software Architecture TI Object Code (.bin) TI Source Code (.c /.h) Customer Code DPD Command Mailbox & Dispatcher DPD State Machine DPD Core 5322 Config C6727 DSP GC5325 CFR-DPD Customer Host Code DPD Command API UART Host µc System TI provides DSP Firmware for Flash Boot TI provides DPD Command API through UART Customer develops Host code that accesses DPD commands via APIs Flash SDRAM

GC5325 2 x 2 MIMO Transmit Solution Architecture * It is possible to time-share the feedback signal chain (ADS6B149, Mixer, Filters) and DSP

GC5325SEK System Architecture System level performance can be evaluated in the manufacturer s design with the easy-to-use GC5325 system evaluation kit (GC5325SEK). The GC5325SEK consists of a dual-transmitter architecture, supporting transmit diversity, multipleinput and multiple-output (MIMO), and beamforming for smart antenna applications. In addition, customers can save four man months of development time by leveraging the GC5325SEK architecture to implement their own design.

GC5325SEK System Architecture 2 Antenna/PAs supported by: 2 GC5325 1 TMS320C6727 DSP 128MB Flash SDRAM UART Serial/Parallel 2 TX Path DAC5682Z TRF3703 RF variable attenuator 1 Feedback Path RF variable attenuator Mixer ADS61B49 TSW3100 Pattern Generator FPGA GC5325EVM GC5325 C6727 DSP GC5325 CDCM 7005 DAC5682Z ADS61B49 DAC5682Z VCXO Transmit Path #1 TRF703 Feedback Path Transmit Path #2 PA PA

GC5325 EVM Support 100 MHz DPD Bandwidth Supports 700 to 1400MHz and 1600 to 3500 MHz Bands Evaluation Process 1. Customer supplies a composite (after DUC) input signal at any sample rate 2. Input signal resamples to 61.44 MSPS input rate and loaded to EVM 3. Crest Factor Block Auto Configuration 4. Load GC5325 EVM system 5. Setup PA test hardware, adjust PA input power, auto-calibrate feedback gain 6. Start/Stop/Hold DPD

GC5322 vs GC5325 Product Comparison Feature GC5322 GC5325 DSP I/F UHPI UART DSP Boot Host Processor Flash DUC Function Y N CFR Function Y Y DPD Function Y Y DPD Signal Bandwidth > 20MHz > 20MHz Applications Support High Moderate Pricing @ 1K units $99 $89

GC5325 Development Schedule Datasheet Available Samples Available RTM Complete EVM ($4,999 USD) March 2009

Summary The GC5325 is a highly integrated Digital Pre-Distortion IC solution designed to improve the PA efficiency and ACLR performance for wideband cellular radio card designs. The GC5325 implements two critical transmit digital functions (CFR, DPD) in a single device. The GC5325 DPD architecture reduces radio card design complexity, development time, implementation size, and overall bill-of-material (BOM) costs. The GC5325 solution is DSP-based and flexible. The GC5325 is suitable for multiple PA architectures as well as existing and emerging wireless standards. The GC5325SEK evaluation system offers fast time-to-market and reduced risk as part of a complete TI-supplied signal chain solution.