L6385 HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER

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Transcription:

HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER HIGH VOLTAGE RAIL UP TO 600 V dv/dt IMMUNITY +- 50 V/nsec IN FULL TEM- PERATURE RANGE DRIVER CURRENT CAPABILITY: 400 ma SOURCE, 650 ma SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN UNDER VOLTAGE LOCK OUT ON LOWER AND UPPER DRIVING SECTION INTERNAL BOOTSTRAP DIODE OUTPUTS IN PHASE WITH INPUTS BLOCK DIAGRAM SO D ORDERING NUMBERS: Minidip DESCRIPTION The is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. BOOTSTRAP DRIVER Vboot V CC HIN 3 2 UV DETECTION LOGIC UV DETECTION LEVEL SHIFTER R R S V CC DRIVER 6 OUT H.V. Cboot TO LOAD LIN 1 5 LVG LVG DRIVER 4 GND D9IN514B June 1999 1/9

ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vout Output Voltage -3 to Vboot - 1 V Vcc Supply Voltage - 0.3 to +1 V Vboot Floating Supply Voltage - 1 to 61 V Vhvg Upper Gate Output Voltage - 1 to Vboot V Vlvg Lower Gate Output Voltage -0.3 to Vcc +0.3 V Vi Logic Input Voltage -0.3 to Vcc +0.3 V dvout/dt Allowed Output Slew Rate 50 V/ns Ptot Total Power Dissipation (Tj = 5 C) 50 mw Tj Junction Temperature 150 C Ts Storage Temperature -50 to 150 C Note: ESD immunity for pins 6, and is guaranteed up to 900V (Human Body Model) PIN CONNECTION LIN 1 Vboot HIN 2 Vcc 3 6 OUT GND 4 5 LVG D9IN51 THERMAL DATA Symbol Parameter SO Minidip Unit R th j-amb Thermal Resistance Junction to Ambient 150 100 C/W PIN DESCRIPTION N. Name Type Function 1 LIN I Lower Driver Logic Input 2 HIN I Upper Driver Logic Input 3 Vcc I Low Voltage Power Supply 4 GND Ground 5 LVG (*) O Low Side Driver Output 6 VOUT O Upper Driver Floating Reference (*) O High Side Driver Output Vboot Bootstrap Supply Voltage (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 2/9

RECOMMENDED OPERATING CONDITIONS Symbol Pin Parameter Test Condition Min. Max. Unit Vout 6 Output Voltage Note 1 50 V Vboot- Floating Supply Voltage Note 1 1 V Vout fsw Switching Frequency,LVG load CL = 1nF 400 khz Vcc 2 Supply Voltage 1 V T j Junction Temperature -45 125 C Note 1: If the condition Vboot - Vout < 1V is guaranteed, Vout can range from -3 to 50V. ELECTRICAL CHARACTERISTICS AC Operation (Vcc = 15V; Tj = 25 C) Symbol Pin Parameter Test Condition Min. Max. Unit ton 1 vs High/Low Side Driver Turn-On Vout = 0V 110 ns Propagation Delay toff 2 vs 5 High/Low Side Driver Turn-Off Vout = 600V 105 ns Propagation Delay tr,5 Rise Time CL = 1000pF 50 ns tf,5 Fall Time CL = 1000pF 30 ns DC OPERATION (Vcc = 15V; Tj = 25 C) Symbol Pin Parameter Test Condition Min. Max. Unit Low Supply Voltage Section Vcc 3 Supply Voltage 1 V Vccth1 Vcc UV Turn On Threshold 9.1 9.6 10.1 V Vccth2 Vcc UV Turn Off Threshold.9.3. V Vcchys Vcc UV Hysteresis 1.3 V Iqccu Undervoltage Quiescent Supply Vcc 9V 150 220 µa Current Iqcc Quiescent Current Vcc = 15V 250 320 µa R dson Bootstrap Driver on Resistance (*) Vcc 12.5V 125 Ω Bootstrapped supply Voltage Section VBS Bootstrap Supply Voltage 1 V VBSth1 VBS UV Turn On Threshold.5 9.5 10.5 V VBSth2 VBS UV Turn Off Threshold.2.2 9.2 V VBShys VBS UV Hysteresis 1.3 V IQBS VBS Quiescent Current ON 200 µa ILK High Voltage Leakage Current VS = VB = 600V 10 µa High/Low Side Driver Iso 5, Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 ma Isi Sink Short Circuit Current VIN = Vil (tp < 10µs) 450 650 ma Logic Inputs Vil 2,3 Low Level Logic Threshold Voltage 1.5 V Vih High Level Logic Threshold Voltage 3.6 V Iih High Level Logic Input Current VIN = 15V 50 0 µa Iil Low Level Logic Input Current VIN = 0V 1 µa (VCC VCBOOT1) (VCC VCBOOT2) (*) RDSON is tested in the following way: RDSON = I 1(V CC,V CBOOT1) I 2(V CC,V CBOOT2) where I1 is pin current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 3/9

Figure 1. Input/Output Timing Diagram HIN LIN LVG D99IN1053 Figure 2. Typical Rise and Fall Times vs. Load Capacitance Figure 3. Quiescent Current vs. Supply Voltage time (nsec) D99IN1054 Iq (µa) D99IN1055 250 10 4 200 150 100 Tr Tf 10 3 10 2 50 0 0 1 2 3 4 5 C (nf) For both high and low side buffers @25 C Tamb 10 0 2 4 6 10 12 14 16 V S (V) BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : C EXT = Q gate V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If has to be supplied for a long time, the CBOOT selection has to take into account also the 4/9

leakage losses. e.g.: steady state consumption is lower than 200µA, so if TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the Figure 4. Bootstrap Driver. drop on the bootstrap DMOS: V drop = I charge R dson V drop = Q gate T charge R dson where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: V drop = 30nC 5µs 125Ω ~ 0.V Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn t allow a sufficient charging time, an external diode can be used. D BOOT V S V BOOT V S V BOOT H.V. H.V. C BOOT C BOOT V OUT V OUT TO LOAD TO LOAD LVG LVG a b D99IN1056 Figure 5. Turn On Time vs. Temperature Figure 6. Turn Off Time vs. Temperature 250 200 250 200 Ton (ns) 150 100 Toff (ns) 150 100 50 50 0 0 5/9

Figure. VBOOT UV Turn On Threshold vs. Temperature Vbth1 (V) 13 12 11 10 9 6 5 Figure 10. Vcc UV Turn Off Threshold vs. Temperature 11 Vccth2(V) 10 9 6 Figure. VBOOT UV Turn Off Threshold vs. Temperature Vbth2 (V) Vccth1(V) 14 13 12 11 10 9 6 Figure 9. Vcc UV Turn On Threshold vs. Temperature 13 12 11 10 9 Figure 11. Output Source Current vs. Temperature current (ma) Figure 12. Output Sink Current vs. Temperature current (ma) 1000 00 600 400 200 0 1000 00 600 400 200 0 6/9

DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.00 0.012 D 10.92 0.430 E.95 9.5 0.313 0.34 e 2.54 0.100 e3.62 0.300 e4.62 0.300 F 6.6 0.260 I 5.0 0.200 L 3.1 3.1 0.125 0.150 Z 1.52 0.060 Minidip /9

DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.5 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.5 0.026 0.033 b 0.35 0.4 0.014 0.019 b1 0.19 0.25 0.00 0.010 C 0.25 0.5 0.010 0.020 c1 45 (typ.) D (1) 4. 5.0 0.19 0.19 E 5. 6.2 0.22 0.244 e 1.2 0.050 e3 3.1 0.150 F (1) 3. 4.0 0.15 0.15 L 0.4 1.2 0.016 0.050 M 0.6 0.024 S (max.) OUTLINE AND MECHANICAL DATA SO (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). /9

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9

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