80V/.5A Peak, High FrequencyFull Bridge FET Driver NOT RECOMMENDED FOR NEW DESIGNS POSSIBLE SUBSTITUTE PRODUCT INTERSIL PART NUMBER HIP4080A DATASHEET FN78 Rev.00 The HIP4080 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 0 lead plastic SOIC and DIP packages. The HIP4080 includes an input comparator, used to facilitate the hysteresis and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to MHz, the HIP4080 is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080 can also drive medium voltage brush motors, and two HIP4080s can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. The similar HIP408 IC allows independent control of all 4 FETs in an Full Bridge configuration. See also, Application Note AN94 for the HIP4080. Similar part, HIP4080A, includes under voltage circuitry which doesn t require the circuitry shown in Figure 0 of this data sheet. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE HIP4080IP -40 to 85 0 Lead PDIP E0. PKG. NO. HIP4080IB -40 to 85 0 Lead SOIC M0. Features Drives N-Channel FET Full Bridge Including High Side Chop Capability Bootstrap Supply Max Voltage to 95V DC Drives 000pF Load at MHz in Free Air at 50 o C with Rise and Fall Times of 0ns (Typ) User-Programmable Dead Time Charge-Pump and Bootstrap Maintain Upper Bias Supplies (Disable) Pin Pulls Gates Low Input Logic Thresholds Compatible with 5V to 5V Logic Levels Very Low Power Consumption Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S. Pinout HIP4080 (0-LEAD PDIP, SOIC) TOP VIEW BHB 0 BHO HEN 9 BHS 8 BLO V SS 4 7 BLS OUT 5 6 IN+ 6 5 V CC IN- 7 4 ALS HDEL 8 ALO LDEL 9 AHS AHB 0 AHO FN78 Rev.00 Page of
Application Block Diagram 80V V BHO BHS HEN BLO HIP4080 LOAD IN+ IN- ALO AHS AHO GND GND Functional Block Diagram (/ HIP4080) 0 AHB HIGH VOLTAGE BUS 80V DC CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER AHO C BS 6 AHS HEN TURN-ON DELAY 5 V CC D BS TO (PIN 6) OUT IN+ IN _ 5 6 7 + - TURN-ON DELAY DRIVER 4 ALO ALS C BF +V DC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4 FN78 Rev.00 Page of
Typical Application (Hysteresis Mode Switching) 80V V BHB HEN BHO BHS BLO 0 9 8 LOAD 4 V SS BLS 7 5 OUT 6 6V 6 IN+ V CC 5 V IN 7 8 IN- HDEL ALS ALO 4 9 LDEL AHS 0 AHB AHO GND - + 6V GND FN78 Rev.00 Page of
Absolute Maximum Ratings Supply Voltage, and V CC................... -0.V to 6V Logic I/O Voltages....................... -0.V to +0.V Voltage on AHS, BHS... -6.0V (Transient) to 80V (5 o C to 5 o C) Voltage on AHS, BHS... -6.0V (Transient) to 70V (-55 o C to 5 o C Voltage on ALS, BLS....... -.0V (Transient) to +.0V (Transient) Voltage on AHB, BHBV AHS, BHS -0.V to V AHS, BHS +6VVoltage on Voltage on ALO, BLO............V ALS, BLS -0.V to V CC +0.V Voltage on AHO, BHO...... V AHS, BHS -0.V to V AHB, BHB +0.V Input Current, HDEL and LDEL.................. -5mA to 0mA Phase Slew Rate.................................. 0V/ns All Voltages relative to pin 4, V SS, unless otherwise specified. Thermal Information Thermal Resistance (Typical, Note )............... JA ( o C/W) SOIC Package...................................... 85 PDIP Package...................................... 75 Maximum Power Dissipation at 85 o C SOIC Package.................................. 470mW DIP Package................................... 50mW Storage Temperature Range................. -65 o C to 50 o C Operating Max. Junction Temperature.................. 5 o C Lead Temperature (Soldering 0s)..................... 00 o C (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, and V CC................... +8V to +5V Voltage on ALS, BLS......................... -.0V to +.0V Voltage on AHB, BHB....... V AHS, BHS +5V to V AHS, BHS +5V Input Current, HDEL and LDEL................-500 A to -50 A Operating Ambient Temperature Range.......... -40 o C to 85 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A =5 o C, Unless Otherwise Specified T J = 5 o C T J = - 40 o C TO 5 o C PARAMETERS SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS MIN TYP MAX MIN MAX UNITS Quiescent Current I DD IN- =.5V, Other Inputs = 0V 8 0.5 7 4 ma Operating Current I DDO Outputs switching f = 500kHz 9 4 8 5 ma V CC Quiescent Current I CC IN- =.5V, Other Inputs = 0V, I ALO = I BLO = 0-5 80-00 A V CC Operating Current I CCO f = 500kHz, No Load.5.0 0.8 ma AHB, BHB Quiescent Current - Qpump Output Current I AHB, I BHB IN- =.5V, Other Inputs = 0V, I AHO = I BHO = 0, = V CC = V AHB = V BHB = 0V -50-0 -5-60 -0 A AHB, BHB Operating Current I AHBO, I BHBO f = 500kHz, No Load 0.5 0.9. 0.4.7 ma AHS, BHS, AHB, BHB Leakage Current I HLK V AHS = V BHS = V AHB = V BHB = 95V - 0.0.0-0 A AHB-AHS, BHB-BHS Qpump Output Voltage V AHB - V AHS V BHB - V BHS I AHB = I AHB = 0, No Load.5.6 4.0 0.5 4.5 V INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage V OS Over Common Mode Voltage Range -0 0 +0-5 +5 mv Input Bias Current I IB 0 0.5 0 4 A Input Offset Current I OS - 0 + - + A Input Common Mode Voltage Range CMVR - -.5 -.5 V Voltage Gain AVOL 0 5-0 - V/mV FN78 Rev.00 Page 4 of
Electrical Specifications = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 00K, and T A =5 o C, Unless Otherwise Specified (Continued) T J = 5 o C T J = - 40 o C TO 5 o C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS OUT High Level Output Voltage V OH IN+ > IN-, I OH = -00 A -0.4 - - - 0.5 - V OUT Low Level Output Voltage V OL IN+ < IN-, I OL = 00 A - - 0. - 0.4 V High Level Output Current I OH VOUT = 6V -9-7 -4 - - ma Low Level Output Current I OL VOUT = 6V 8 0 5 4 ma INPUT PINS: Low Level Input Voltage V IL Full Operating Conditions - -.0-0.8 V High Level Input Voltage V IH Full Operating Conditions.5 - -.7 - V Input Voltage Hysteresis - 5 - - - mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions -0-00 -75-5 -65 A High Level Input Current I IH V IN = 5V, Full Operating Conditions - - + -0 +0 A INPUT PINS: HEN Low Level Input Voltage V IL Full Operating Conditions - -.0-0.8 V High Level Input Voltage V IH Full Operating Conditions.5 - -.7 - V Input Voltage Hysteresis - 5 - - - mv Low Level Input Current I IL V IN = 0V, Full Operating Conditions -60-00 -50-70 -0 A High Level Input Current I IH V IN = 5V, Full Operating Conditions - - + -0 +0 A TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V I HDEL = I LDEL = -00 A 4.9 5. 5. 4.8 5.4 V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage V OL I OUT = 00mA.70 0.85.0 0.5. V High Level Output Voltage V CC - V OH I OUT = -00mA 0.8 0.95. 0.5. V Peak Pull-up Current I O + V OUT = 0V.7.6.8.4 4. A Peak Pull-down Current I O - V OUT = V.7.4...6 A Switching Specifications = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF, and T A = 5 o C, Unless Otherwise Specified T J = 5 o C T J = - 40 o C TO 5 o C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) T LPHL - 40 70-90 ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) T HPHL - 50 80-0 ns Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) T LPLH R HDEL = R LDEL = 0K - 45 70-90 ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) T HPLH R HDEL = R LDEL = 0K - 70 0-40 ns Rise Time T r - 0 5-5 ns Fall Time T f - 0 5-5 ns Turn-on Input Pulse Width T PWIN-ON R HDEL = R LDEL = 0K 50 - - 50 - ns Turn-off Input Pulse Width T PWIN-OFF R HDEL = R LDEL = 0K 40 - - 40 - ns FN78 Rev.00 Page 5 of
Switching Specifications = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL = R LDEL = 0K, C L = 000pF, and T A = 5 o C, Unless Otherwise Specified (Continued) T J = 5 o C T J = - 40 o C TO 5 o C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Disable Turn-off Propagation Delay ( - Lower Outputs) Disable Turn-off Propagation Delay ( - Upper Outputs) Disable to Lower Turn-on Propagation Delay ( - ALO and BLO) T LOW - 45 75-95 ns T HIGH - 55 85-05 ns T DLPLH - 5 70-90 ns Refresh Pulse Width (ALO and BLO) T REF-PW 60 60 80 40 40 ns Disable to Upper Enable ( - AHO and BHO) T UEN - 5 500-550 ns HEN-AHO, BHO Turn-off, Propagation Delay T HEN-PHL R HDEL = R LDEL = 0K - 5 70-90 ns HEN-AHO, BHO Turn-on, Propagation Delay T HEN-PLH R HDEL = R LDEL = 0K - 60 90-0 ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN ALO AHO BLO BHO X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins and 0) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 5V (no greater than ). able input. Logic level input that when taken high sets all four outputs low. high overrides all other inputs. When is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 5V (no greater than ). 4 V SS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. (Pin ) high level will override IN+/IN- control for all outputs. HEN (Pin ) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.V. FN78 Rev.00 Page 6 of
HIP4080 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.V. 0 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 0 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately.8v. AHO A High-side Output. Connect to gate of A High-side power MOSFET. AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 4 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 5 V CC Positive supply to gate drivers. Must be same potential as (Pin 6). Connect to anodes of two bootstrap diodes. 6 Positive supply to lower gate drivers. Must be same potential as V CC (Pin 5). De-couple this pin to V SS (Pin 4). 7 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 8 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 9 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 0 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN78 Rev.00 Page 7 of
HIP4080 Timing Diagrams = 0 HEN = IN+ > IN- T HPHL T DT T LPLH ALO AHO BLO BHO T T HPLH LPHL T T r T DT f (0% - 90%) (90% - 0%) FIGURE. BI-STATE MODE T HEN-PHL T HEN-PLH = 0 HEN IN+ > IN- ALO AHO BLO BHO FIGURE. HIGH SIDE CHOP MODE HEN = IN+ > IN- T DLPLH T REF-PW T ALO AHO BLO BHO T UEN FIGURE. ABLE FUNCTION FN78 Rev.00 Page 8 of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified 4.0 I DD SUPPLY CURRENT (ma).0 0.0 8.0 6.0 4.0 SUPPLY CURRENT (ma).5.0.5.0 0.5.0 8 0 4 SUPPLY VOLTAGE (V) 0 00 400 600 800 000 SWITCHING FREQUENCY (khz) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 5. I DDO, NO-LOAD I DD SUPPLY CURRENT vs FREQUENCY (khz) FLOATING SUPPLY BIAS CURRENT (ma) 0.0 5.0 0.0 5.0 0.0 5.0 0.0 0 00 00 00 400 500 600 700 800 900 000 I CC SUPPLY CURRENT (ma) 5.0 5 o C 75 o C 4.0 5 o C 0 o C.0-40 o C.0.0 0.0 0 00 00 00 400 500 600 700 800 900 000 SWITCHING FREQUENCY (khz) SWITCHING FREQUENCY (khz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 000pF) FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FREQUENCY (khz) TEMPERATURE FLOATING SUPPLY BIAS CURRENT (ma).8.4.0 0.6 0. -0. 0 00 400 600 800 000 COMPARATOR INPUT CURRENT ( A).0 0.5 FREQUENCY (khz) FIGURE 8. I AHB, I BHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9. COMPARATOR INPUT CURRENT I L vs TEMPERATURE AT V CM = 5V FN78 Rev.00 Page 9 of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified (Continued) -90-80 LOW LEVEL INPUT CURRENT ( A) -00-0 LOW LEVEL INPUT CURRENT ( A) -90-00 -0-0 -0-50 -5 0 5 50 75 00 5-0 FIGURE 0. LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE FIGURE. HEN LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE NO-LOAD FLOATING CHARGE PUMP VOLTAGE 5.0 4.0.0.0.0 0.0 PROPAGATION DELAY (ns) 80 70 60 50 40 0 FIGURE. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE FIGURE. UPPER ABLE TURN-OFF PROPAGATION DELAY T HIGH vs TEMPERATURE FN78 Rev.00 Page 0 of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified (Continued) 400 80 PROPAGATION DELAY (ns) 80 60 40 0 PROPAGATION DELAY (ns) 70 60 50 40 00 0 FIGURE 4. ABLE TO UPPER ENABLE T UEN PROPAGATION DELAY vs TEMPERATURE 75 FIGURE 5. LOWER ABLE TURN-OFF PROPAGATION DELAY T LOW vs TEMPERATURE 80 REFRESH PULSE WIDTH (ns) 5 75 5 PROPAGATION DELAY (ns) 70 60 50 40 0 75 0 FIGURE 6. T REF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 7. ABLE TO LOWER ENABLE T DLPLH PROPAGATION DELAY vs TEMPERATURE FN78 Rev.00 Page of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified (Continued) 90.0 90.0 PROPAGATION DELAY (ns) 80.0 70.0 60.0 50.0 PROPAGATION DELAY (ns) 80.0 70.0 60.0 50.0 40.0 40.0 FIGURE 8. UPPER TURN-OFF PROPAGATION DELAY T HPHL vs TEMPERATURE FIGURE 9. UPPER TURN-ON PROPAGATION DELAY T HPLH vs TEMPERATURE 90.0 90.0 PROPAGATION DELAY (ns) 80.0 70.0 60.0 50.0 PROPAGATION DELAY (ns) 80.0 70.0 60.0 50.0 40.0 40.0 FIGURE 0. LOWER TURN-OFF PROPAGATION DELAY T LPHL vs TEMPERATURE.5 FIGURE. LOWER TURN-ON PROPAGATION DELAY T LPLH vs TEMPERATURE.5 GATE DRIVE FALL TIME (ns).5.5 0.5 9.5 TURN-ON RISE TIME (ns).5.5 0.5 9.5 8.5 8.5 JUNCTION TEMPERATURE (C) FIGURE. GATE DRIVE FALL TIME T F vs TEMPERATURE FIGURE. GATE DRIVE RISE TIME T R vs TEMPERATURE FN78 Rev.00 Page of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified (Continued) 6.0 500 HDEL, LDEL INPUT VOLTAGE (V) 5.5 5.0 4.5 V CC - V OH (mv) 50 000 750 500 50-40 o C 0 o C 5 o C 75 o C 4.0 5 o C 0 6 8 0 4 BIAS SUPPLY VOLTAGE (V) FIGURE 4. V LDEL, V HDEL VOLTAGE vs TEMPERATURE FIGURE 5. HIGH LEVEL OUTPUT VOLTAGE, V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT 00mA 500.5 V OL (mv) 50 000 750 500 50-40 o C 0 o C 5 o C 75 o C GATE DRIVE SINK CURRENT (A).0.5.0.5.0 0.5 0 5 o C 6 8 0 4 BIAS SUPPLY VOLTAGE (V) 0.0 6 7 8 9 0 4 5 6, V CC, V AHB, V BHB (V) FIGURE 6. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERATURE AT 00mA FIGURE 7. PEAK PULLDOWN CURRENT I O vs BIAS SUPPLY VOLTAGE FN78 Rev.00 Page of
Typical Performance Curves = V CC = V AHB = V BHB = V, V SS = V ALS = V BLS = V AHS = V BHS = 0V, R HDEL =R LDEL = 00K, and T A = 5 o C, Unless Otherwise Specified (Continued).5 500 GATE DRIVE SINK CURRENT (A).0.5.0.5.0 0.5 LOW VOLTAGE BIAS CURRENT (ma) 00 00 50 0 0 5 0.5 0. 0,000,000,000 00 0.0 6 7 8 9 0 4 5 6, V CC, V AHB, V BHB (V) 0. 5 0 0 50 00 00 500 000 SWITCHING FREQUENCY (khz) FIGURE 8. PEAK PULLUP CURRENT I O+ vs SUPPLY VOLTAGE FIGURE 9. LOW VOLTAGE BIAS CURRENT I DD AND I CC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 000 50 500 LEVEL-SHIFT CURRENT ( A) 00 00 50 0 0 5 80V 60V 40V 0V 5 0 0 50 00 00 500 000 SWITCHING FREQUENCY (khz) DEAD-TIME (ns) 0 90 60 0 0 0 50 00 50 00 50 HDEL/LDEL RESISTANCE (k ) FIGURE 0. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE HIP4080 Power-up Application Information The HIP4080 H-Bridge Driver IC requires external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-Bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. The HIP4080 does not have an input protocol like the HIP408 that keeps both lower power MOSFETs off other than through the pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure. Pulling LDEL to will indefinitely delay the lower turn-on delays through the input comparator and will FIGURE. MINIMUM DEAD-TIME vs DEL RESISTANCE keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e. = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure. FN78 Rev.00 Page 4 of
ENABLE BHB HEN BHO 0 BHS 9 BLO 8 56K 8.V 56K N906 00K 00K 0. F RDEL RDEL 4 V SS 5 OUT 6 IN+ 7 IN- 8 HDEL 9 LDEL 0 AHB BLS 7 6 V CC 5 ALS 4 ALO AHS AHO FIGURE. V, FINAL VALUE 8.V TO 9.V (ASSUMING 5% ZENER TOLERANCE) LDEL =0ms t t 5.V NOTES:. Between t and t the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the under-voltage circuit is satisfied, the ENABLE pin will initiate the 0ms time delay during which the IN+ and IN- pins must cycle at least once.. Another product, HIP4080A, incorporates undervoltage circuitry which eliminates the need for the above power up circuitry. FIGURE. TIMING DIAGRAM FOR FIGURE FN78 Rev.00 Page 5 of
FN78 Rev.00 Page 6 of IN IN CONTROL LOGIC SECTION 5 U CD4069UB U CD4069UB U CD4069UB U CD4069UB 6 0 R9 JMPR OUT/BLI JMPR IN+/ALI JMPR HEN/BHI JMPR4 IN-/AHI 56K 8.V 56K +V JMPR5 R CW N906 00K R4 CW + C6 ENABLE DRIVER SECTION CR C C5 CR HIP4080/8 U C4 BHB HEN/BHI BHO 0 BHS 9 BLO 8 4 5 6 7 8 9 0 V SS OUT/BLI IN+/ALI IN-/AHI HDEL LDEL AHB BLS V CC ALS ALO AHS AHO 7 6 5 4 +V TO I U 4 CD4069UB O 0.MFD 9 ALS CX R R R R4 8 CD4069UB BLS FIGURE 4. HIP4080 EVALUATION PC BOARD SCHEMATIC U O Q Q CY POWER SECTION R0 L C Q Q4 C8 R L C B+ AO BO COM NOTES: 4. Circuit inside dashed area must be hardwired and is not included on the evaluation board. 5. Device CD4069UB PIN 7 = COM, Pin 4 = +V. 6. Components L, L, C, C, CX, CY, R0, R, are not supplied. refer to Application Note for description of input logic operation to determine jumper locations for JMPR - JMPR4. HIP4080
C AO L C JMPR JMPR JMPR JMPR4 R Q JMPR5 R7 R8 R6 R L GND +V B+ U U CR C4 C R4 BO R R Q CR R R4 BLS Q4 R0 IR O C8 C5 CX CY C7 C6 R9 IN IN + + LDEL BHO Q COM BLO BLS ALS ALO AHO HDEL HIP4080/8 O ALS FIGURE 5. HIP4080 EVALUATION BOARD SILKSCREEN FN78 Rev.00 Page 7 of
Supplemental Information for HIP4080 and HIP408 Power-Up Application The HIP4080 and HIP408 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. HIP408 The HIP408 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 6. As the /V CC supply ramps from zero up, the voltage is below its input threshold of.7v due to the R/R resistor divider. When /V CC exceeds approximately 9V to 0V, becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to reaching its threshold level of.7v while /V CC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the pin low. HIP4080 The HIP4080 does not have an input protocol like the HIP408 that keeps both lower power MOSFETs off other than through the pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 7. Pulling LDEL to will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e., = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 7. ENABLE R 5K R.K BHB BHI 4 V SS 5 BLI 6 ALI BHO 0 BHS 9 BLO 8 BLS 7 6 V CC 5 ENABLE R 5K R.K BHB BHI 4 V SS 5 BLI 6 ALI BHO 0 BHS 9 BLO 8 BLS 7 6 V CC 5 7 AHI ALS 4 7 AHI ALS 4 8 HDEL ALO 8 HDEL ALO 9 LDEL 0 AHB AHS AHO 9 LDEL 0 AHB AHS AHO FIGURE 6. ENABLE BHB HEN BHO 0 BHS 9 BLO 8 56K 8.V 56K N906 00K 00K 0. F RDEL RDEL 4 V SS 5 OUT 6 IN+ 7 IN- 8 HDEL 9 LDEL 0 AHB BLS 7 6 V CC 5 ALS 4 ALO AHS AHO FIGURE 7. FN78 Rev.00 Page 8 of
Timing Diagrams V, FINAL VALUE V, FINAL VALUE 8.V TO 9.V (ASSUMING 5% ZENER TOLERANCE) 8.5V TO 0.5V (ASSUMES 5% RESISTORS) ALI, BLI LDEL.7V =0ms t t 5.V NOTE: 7. ALI and/or BLI may be high after t, whereupon the ENABLE pin may also be brought high. FIGURE 8. NOTE: 8. Between t and t the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important). If the ENABLE pin is low after the undervoltage circuit is satisfied, the ENABLE pin will initiate the 0ms time delay during which the IN+ and IN- pins must cycle at least once. FIGURE 9. FN78 Rev.00 Page 9 of
N Small Outline Plastic Packages (SOIC) INDEX AREA e D B 0.5(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.6mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ 0.5(0.00) M B L M h x 45 o C M0. (JEDEC MS-0-AC ISSUE C) 0 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.096 0.04.5.65 - A 0.0040 0.08 0.0 0.0 - B 0.0 0.000 0. 0.5 9 C 0.009 0.05 0. 0. - D 0.496 0.58.60.00 E 0.94 0.99 7.40 7.60 4 e 0.050 BSC.7 BSC - H 0.94 0.49 0.00 0.65 - h 0.00 0.09 0.5 0.75 5 L 0.06 0.050 0.40.7 6 N 0 0 7 0 o 8 o 0 o 8 o - Rev. 0 /9 FN78 Rev.00 Page 0 of
Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B N N/ B D e D -C- -A- NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 95. 4. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of 0.00-0.045 inch (0.76 -.4mm). E -B- A 0.00 (0.5) M C A A L B S A e C E C L e A e B C E0. (JEDEC MS-00-AD ISSUE D) 0 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.0-5. 4 A 0.05-0.9-4 A 0.5 0.95.9 4.95 - B 0.04 0.0 0.56 0.558 - B 0.045 0.070.55.77 8 C 0.008 0.04 0.04 0.55 - D 0.980.060 4.89 6.9 5 D 0.005-0. - 5 E 0.00 0.5 7.6 8.5 6 E 0.40 0.80 6.0 7. 5 e 0.00 BSC.54 BSC - e A 0.00 BSC 7.6 BSC 6 e B - 0.40-0.9 7 L 0.5 0.50.9.8 4 N 0 0 9 Rev. 0 /9 Copyright Intersil Americas LLC 00. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN78 Rev.00 Page of