Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain to Source Voltage V DSS 6 V Gate to Source Voltage V GS ±2 V Continuous Drain T A = 25 C I D 5.7 A Current R JA (Note ) T A = C 4. Power Dissipation R JA (Note ) Continuous Drain Current R JC (Note ) Power Dissipation R JC (Note ) Steady State T A = 25 C P D 3.2 W T A = C.6 T C = 25 C I D 2 A T C = C 4 T C = 25 C P D 4 W T C = C 2 Pulsed Drain Current t p = s I DM 76 A Operating Junction and Storage Temperature T J, T stg 55 to +75 Source Current (Body Diode) I S 2 A Single Pulse Drain to Source Avalanche L =. mh E AS 45 mj Energy I AS 3 A Lead Temperature for Soldering Purposes (/8 from case for s) T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction to Case Steady R JC 3.8 C/W State (Note ) Junction to Ambient Steady State (Note ) R JA 47. Surface mounted on FR4 board using in sq pad size (Cu area =.27 in sq [2 oz] including traces. C V (BR)DSS R DS(on) MAX I D MAX 6 V G (4) WDFN8 ( 8FL) CASE 5AB 52 m @ V 72 m @ 4.5 V P Channel MOSFET D (5 8) S (,2,3) ORDERING INFORMATION 2 A (Note: Microdot may be in either location) Device Package Shipping NTTFS56PLTAG NTTFS56PLTWG MARKING DIAGRAM S D S 56 D S AYWW D G D 56 = Specific Device Code A = Assembly Location Y = Year WW = Work Week = Pb Free Package WDFN8 (Pb Free) WDFN8 (Pb Free) 5/Tape & Reel 5/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8/D. Semiconductor Components Industries, LLC, 2 November, 2 Rev. Publication Order Number: NTTFS56PL/D
ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = 25 A 6 V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J 69.7 mv/ C Zero Gate Voltage Drain Current I DSS VGS = V, V DS = 6 V. A Gate to Source Leakage Current I GSS V DS = V, V GS = ±2 V ± na ON CHARACTERISTICS (Note 2) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = 25 A 3 V Negative Threshold Temperature Coefficient V GS(TH) /T J 6.2 mv/ C Drain to Source On Resistance R DS(on) V GS = V I D = 6 A 37 52 m V GS = 4.5 V I D = 4.4 A 5 72 Forward Transconductance g FS V DS = 5 V, I D = 6 A S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance C iss 258 pf Output Capacitance C oss V GS = V, f =. MHz, V DS = 3 V 27 Reverse Transfer Capacitance C rss 84 Total Gate Charge Q G(TOT) V GS = V, V DS = 48 V, I D = 5 A 25 nc Threshold Gate Charge Q G(TH) V GS = 4.5 V, V DS = 48 V, I D = 5 A 4 Gate to Source Charge Q GS 4 Gate to Drain Charge Q GD V GS = 4.5 V, V DS = 48 V, I D = 5 A 7 nc Plateau Voltage V GP 3. V Gate Resistance R G 5.3 SWITCHING CHARACTERISTICS (Note 3) Turn On Delay Time t d(on) Rise Time t r V GS = 4.5 V, V DS = 48 V, 58 Turn Off Delay Time t d(off) I D = 5 A, R G = 6 3 Fall Time t f 37 DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD VGS = V, I S = 5 A Reverse Recovery Time t RR 5 ns.79.2 V.64 Charge Time t a V GS = V, d IS /d t = A/ s, 5 Discharge Time t b I S = 5 A 5 2 ns Reverse Recovery Charge Q RR 9 nc 2. Pulse Test: pulse width 3 s, duty cycle 2%. 3. Switching characteristics are independent of operating junction temperatures. 2
TYPICAL CHARACTERISTICS I D, DRAIN CURRENT (A) 4 V GS = V V GS = 4.5 V 3 V GS = 4 V 2 V GS = 3.5 V V GS = 3 V 2 3 4 5 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. On Region Characteristics I D, DRAIN CURRENT (A) 4 V DS V 3 2 T J = 55 C 2 3 4 5 6 V GS, GATE TO SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ).75.65.55.45 I D = 6 A.35 2 4 6 8 V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On Resistance vs. Gate to Source Voltage R DS(on), DRAIN TO SOURCE RESISTANCE ( ).8.7.6.5.4 V GS = 4.5 V V GS = V.3 5 5 2 25 3 35 4 I D, DRAIN CURRENT (A) Figure 4. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RES- ISTANCE (NORMALIZED) 2..8.6.4.2..8 I D = 4.4 A V GS = 4.5 V.6 5 25 25 5 75 25 5 75 T J, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance Variation with Temperature I DSS, LEAKAGE (na),, V GS = V T J = 5 C 2 3 4 5 6 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 6. Drain to Source Leakage Current vs. Voltage 3
TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) 8 6 4 2 8 6 C iss V GS = V V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Capacitance Variation V GS, GATE TO SOURCE VOLTAGE (V) 4 2 V DS = 48 V 2 I C D = 5 A oss T C J = 25 C rss 2 3 4 5 6 5 5 2 25 8 6 4 Q gs Q gd Q T Qg, TOTAL GATE CHARGE (nc) Figure 8. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = 48 V I D = 5 A V GS = 4.5 V t d(on) t r t f t d(off) I S, SOURCE CURRENT (A) 4 3 2 V GS = V R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance.5.6.7.8.9.. V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current I D, DRAIN CURRENT (A) V GS = V Single Pulse T C = 25 C ms ms dc s s R DS(on) Limit Thermal Limit Package Limit.. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. Maximum Rated Forward Biased Safe Operating Area E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 45 3 5 25 5 75 25 5 75 T J, STARTING JUNCTION TEMPERATURE ( C) Figure 2. Maximum Avalanche Energy vs. Starting Junction Temperature 4
TYPICAL CHARACTERISTICS R JA (t) D =.5 D =.2 D =. D =.5 D =.2 D =.. Single Pulse....... PULSE TIME (sec) Figure 3. Thermal Response 5
PACKAGE DIMENSIONS. C. C 8X. C A B.5 C 4X L 2X.2 C D A B 2X D 8 7 6 5 E E 2 3 4 c TOP VIEW A SIDE VIEW DETAIL A e/2 4 K.2 WDFN8 3.3x3.3,.65P CASE 5AB ISSUE C C 6X e DETAIL A 4X A C SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, 994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. PACKAGE OUTLINE MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A.7.75.8.28.3.3 A..5..2 b.23.3.4.9.2.6 c.5.2.25.6.8. D 3.3 BSC.3 BSC D 2.95 3.5 3.5.6.2.24 D2.98 2. 2.24.78.83.88 E 3.3 BSC.3 BSC E 2.95 3.5 3.5.6.2.24 E2.47.6.73.58.63.68 E3.23.3.4.9.2.6 e.65 BSC.26 BSC G.3.4.5.2.6.2 K.64.25 L.3.43.56.2.7.22 L.6.3.2.2.5.8 M.4.5.6.55.59.63 2 2 SOLDERING FOOTPRINT* 8X.42.65 PITCH 4X.66 E2 E3 M G 8 5 D2 BOTTOM VIEW L.75.57 2.3 3.6.47 2.37 3.46 DIMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: 33 675 275 or 8 344 386 Toll Free USA/Canada Fax: 33 675 276 or 8 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 79 29 Japan Customer Focus Center Phone: 8 3 587 5 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTTFS56PL/D