DATASHEET LW EMI, SPREAD MDULATING, CLCK GENERATR ICS9730 Features/Benefits ICS9730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal (EMI peak reduction of 7-4 db on 3rd-9th harmonics) through use of Spread Spectrum techniques. ICS9730 focuses on the lower input frequency range of 4.38 to 80.00 MHz with a spread modulation of 20kHz to 40kHz. Specifications Supply Voltages: VDD = 3.3V ±0.3V Frequency range: 4.38 MHz <Fin > 80 MHz Cyc to Cyc jitter: <50ps utput duty cycle 45-55% 0 C to +85 C operation 8-pin SIC Reference input Pin Configuration CLKIN VDD 2 GND 3 CLKUT 4 Functionality 8 Pin SIC * Internal Pull-Up Resistor 8 PD#* 7 SCLK 6 SDATA 5 REF_UT/FS_IN* FSIN_ MHz Spread % default 0 4.38 MHz in --> 27MHz out -0.8 down spread 27.00MHz in --> 27.00MHz out -.25 down spread Block Diagram IDT LW EMI, SPREAD MDULATING, CLCK GENERATR ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTIN CLKIN PWR Input for reference clock. 2 VDD IN Power supply, nominal 3.3V 3 GND UT Ground pin. 4 CLKUT I/ Modulated clock output. 5 REF_UT/FS_IN* I/ Un-modulated 3.3V reference clock output. Frequency select latch input. Refer to the functionality table. 6 SDATA PWR Data pin for SMBus circuitry, 5V tolerant. 7 SCLK PWR Clock pin of SMBus circuitry, 5V tolerant. 8 PD#* PWR Asynchronous active low input pin, with 20Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VC and the crystal are stopped. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 2 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Table : Frequency Configuration (see I2C 0) 4in/27out FS4 FS3 FS2 FS FS0 Sprd Type Sprd % 0 0 0 0 0 0.60 0 0 0 0 0.80 DWN 0 0 0 0.00 SPREAD 0 0 0.25 (-) 0 0 0 0.50 0 0 0 2.00 0 0 0 CENTER 0.50 0 0 SPD (+/-).00 0 0 0 0 DWN 0.60 0 0 0 SPREAD.00 0 0 0 (-) -0.80 0 0 CTR SPD +/-0.3 4in/4out 27in/27out 48in/48out 66in/66out 0 0 0.50 DWN 0 0.75 SPREAD 0 0 2.00 (-) 0 2.50 0 0 0 0 3.00 0 0 0.25 0 0 0 0.40 0 0 0.50 0 0 0 CENTER 0.70 0 0 SPD (+/-).00 0 0.20 0.50 0 0 0 0.60 0 0 0.80 DWN 0 0.00 SPREAD 0.25 (-) 0 0.50 0 2.00 0 CENTER 0.50 SPD (+/-).00 Above is the hard coded 5 bit (32 entry) RM table. FS3:0 are NLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from FS_IN latched input hardware pins. FS_IN FS4. Upon power-up the default is to use hardware selection of FS_IN latched value. FS3 = 0, FS2 = 0, FS = 0, FS0 = upon power-up (refer to the functionality table on page ). To access non-default spread entries in the RM, byte0 programming should be used. In order to change the power up default of FS_IN = (-.25% down spread) to any other spread % entry, first change byte0bit 0 to software selection by switching this bit to a and then program the desired percentage by changing byte0 bits 7:3. IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 3 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address Controller (host) sends the beginning byte location = N Controller (host) sends the byte count = X Controller (host) starts sending N through N+X- each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning = N Data Count = X Beginning N N + X - P stop bit Read Address D5 (H) X Write Address D4 (H) How to Read Controller (host) will send a start bit Controller (host) sends the write address Controller (host) sends the beginning byte location = N Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will send the data byte count = X IDT clock sends N+X- IDT clock sends 0 through X (if X (H) was written to 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning = N RT Repeat start Slave Address RD ReaD N P Not acknowledge stop bit X Data Count=X Beginning N N + X - IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 4 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR 0 Pin # Name Control Function Type 0 PWD Bit 7 - FS0 Spread/FS0 RW Srpead Pecentage Bit 6 - FS Spread/FS RW 0 See Table Bit 5 FS2 Spread/FS2 RW 0 These are I2C bits Bit 4 FS3 Spread/FS3 RW 0 only Bit 3 FS4 FS4 RW 0 Bit 2 PD# Tri_Sate PD# Tri_Sate RW Hi-Z LW Bit Spread Enable Spread Enable RW FF N Bit 0 HW/SW Control Spread Spectrum Control FS 3:4 Hard/Software Select RW HW SW 0 Pin # Name Control Function Type 0 PWD Bit 7 REF_UT REF_UT_Enable RW Disable Enable Bit 6 - REF_UT Slew Rate REF-UT RW Nominal Fast Bit 5 FS-IN_ FS-IN_ Readback R - - X Bit 4 (Reserved) (Reserved) R - - 0 Bit 3 CLK_UT Slew Rate CLK-UT RW Nominal Fast Bit 2 CLK_UT CLK_UT_Enable RW Disable Enable Bit (Reserved) (Reserved) R - - Bit 0 (Reserved) (Reserved) R - - 2 Pin # Name Control Function Type 0 PWD Bit 7 x - (Reserved) - - - Bit 6 x (Reserved) (Reserved) RW Disable Enable Bit 5 x (Reserved) (Reserved) RW Disable Enable Bit 4 x (Reserved) (Reserved) RW Disable Enable Bit 3 x (Reserved) (Reserved) RW Disable Enable Bit 2 x (Reserved) (Reserved) RW Disable Enable Bit x (Reserved) (Reserved) RW Disable Enable Bit 0 x (Reserved) (Reserved) RW Disable Enable 3 Pin # Name Control Function Type 0 PWD Bit 7 X (Reserved) (Reserved) RW - - Bit 6 X (Reserved) (Reserved) RW - - Bit 5 X (Reserved) (Reserved) RW - - Bit 4 X (Reserved) (Reserved) RW - - Bit 3 x (Reserved) (Reserved) RW - - Bit 2 X (Reserved) (Reserved) RW - - Bit X (Reserved) (Reserved) RW - - Bit 0 X (Reserved) (Reserved) RW - - IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 5 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR 4 Pin # Name Control Function Type 0 PWD Bit 7 X (Reserved) (Reserved) RW - - Bit 6 X (Reserved) (Reserved) RW - - Bit 5 X (Reserved) (Reserved) RW - - Bit 4 X (Reserved) (Reserved) RW - - Bit 3 X (Reserved) (Reserved) RW - - Bit 2 X (Reserved) (Reserved) RW - - Bit X (Reserved) (Reserved) RW - - Bit 0 X (Reserved) (Reserved) RW - - 5 Pin # Name Control Function Type 0 PWD Bit 7 X (Reserved) (Reserved) - - - Bit 6 X (Reserved) (Reserved) - - - Bit 5 X (Reserved) (Reserved) - - - Bit 4 X (Reserved) (Reserved) - - - Bit 3 X (Reserved) (Reserved) RW - - Bit 2 X (Reserved) (Reserved) RW - - Bit X (Reserved) (Reserved) RW - - Bit 0 X (Reserved) (Reserved) RW - - 6 Pin # Name Control Function Type 0 PWD Bit 7 X Revision ID Bit 3 (Reserved) R - - Bit 6 X Revision ID Bit 2 (Reserved) R - - Bit 5 X Revision ID Bit (Reserved) R - - Bit 4 X Revision ID Bit 0 (Reserved) R - - Bit 3 X Vendor ID Bit 3 (Reserved) R - - Bit 2 X Vendor ID Bit 2 (Reserved) R - - Bit X Vendor ID Bit (Reserved) R - - Bit 0 X Vendor ID Bit 0 (Reserved) R - - IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 6 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS9730. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics Input/Supply/Common utput Parameters T A = 0-85 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Input High Voltage V IH 2 V DD + 0.3 V Input Low Voltage V IL V SS - 0.3 0.8 V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = 0 V; Inputs with no pull-up resistors -5 ma Powerdown Current I DD3. 3PD 5 ma perating Current I DD3.3P fin = 4.38MHz 2 27 4 ma fin = 66.67MHz 2 32 50 ma Input Frequency Fi V DD = 3.3 V 4.38 MHz Pin Inductance Lpin 7 nh C IN Logic Inputs 5 pf Input Capacitance C UT utput pin capacitance 6 pf C INX X & X2 pins 27 36 45 pf Transition time T tra ns To st crossing of target frequency 3 ms Settling time Ts From st crossing to % target frequency 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target frequency 3 ms Delay t PZH,t PZL utput enable delay (all outputs) 0 ns Guaranteed by design, not 00% tested in production. 2 perating current depends on both the input and output frequencies. The values shown represent the upper and lower extremes. The higher the input/output frequency, the higher the current draw. The relationship is linear. IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 7 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Electrical Characteristics CLKUT T A = 0-85 C; V DD = 3.3V +/-5%; C L = 5 pf (unless otherwise specified) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS utput High Voltage V H 3 I H = - ma 2.4 V utput Low Voltage V L3 I L = ma 0.4 Rise Time tr3 V L = 0.4V, V H = 0.86V 0.5 0.6 ns Fall Time tf3 V H = 0.86V V L = 0.4V 0.5 0.6 ns measurement from differential wavefrom - Duty Cycle d t3 0.35V to +035V 45 50 55 % Jitter, Cycle to cycle t jcyc-cyc V T = 50% 50 50 ps Guaranteed by design, not 00% tested in production. Electrical Characteristics REF T A = 0-85 C; V DD = 3.3V +/-5%; C L = 5 pf (unless otherwise specified) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS utput Frequency F 4.38 MHz utput Impedance R DSP V = V DD *(0.5) 20 48 60 Ω utput High Voltage V H I H = - ma 2.4 V utput Low Voltage V L I L = ma 0.4 V utput High Current I H V H@MIN =.0 V, V H@MAX = 3.35 V -29-23 ma utput Low Current I L V L @ MIN =.95 V, V L @MAX = 0.4 V 29 27 ma Rise Time t r V L = 0.4 V, V H = 2.4 V.2 2 ns Fall Time t f V H = 2.4 V, V L = 0.4 V.2 2 ns Duty Cycle d t V T =.5 V 45 5 55 % Jitter t jcyc-cyc V T =.5 V 05 300 ps Guaranteed by design, not 00% tested in production. IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 8 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Package utline and Package Dimensions (8-pin SIC, 50 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Inches INDEX AREA 2 D E H Symbol Min Max Min Max A.35.75.0532.0688 A 0.0 0.25.0040.0098 B 0.33 0.5.03.020 C 0.9 0.25.0075.0098 D 4.80 5.00.890.968 E 3.80 4.00.497.574 e.27 BASIC 0.050 BASIC H 5.80 6.20.2284.2440 h 0.25 0.50.00.020 L 0.40.27.06.050 α 0 8 0 8 A h x 45 A - C - C e B SEATING PLANE.0 (.004) C L rdering Information Part / rder Number Shipping Packaging Package Temperature 9730AMLF Tubes 8-pin SIC 0 to +85 C 9730AMLFT Tape and Reel 8-pin SIC 0 to +85 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. A is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 9 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR Revision History Rev. B C D E F Issue Date Who Description Page # 06/25/04 Add Lead Free package description to rdering Information 0 06/29/04 Add Revision History table to datasheet. 05/23/05. Revise ABS max ratings. 2. Updated REF Electrical Characteristics table. 3. Updated LF ordering information from "lead free" to "RoHS compliant". 8-0 06/04/08 Updated MLF ordering info 9 06/6/ RDW. Added operating current specs that were inadvertantly ommitted 2. Updated ordering info to latest format 3. Changed CL from "0-20 pf" to 5 pf, 7-9 IDT LW EMI, SPREAD MDULATING, CLCK GENERATR 0 ICS9730 REV F 066
ICS9730 LW EMI, SPREAD MDULATING, CLCK GENERATR SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.idt.com For Sales 800-345-705 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. www.idt.com 20 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA