Week 9a OUTLINE MOSFET I vs. V GS characteristic Circuit models for the MOSFET resistive switch model small-signal model Reading Rabaey et al.: Chapter 3.3.2 Hambley: Chapter 12 (through 12.5); Section 10.8 (Linear Small-Signal Equivalent Circuits) Week 9a, Slide 1
I vs. V S Characteristics The MOSFET I -V S curve consists of two regions: 1) Resistive or Triode Region: 0 < V S < V GS V T I = k n where W L k n VGS V = µ C n ox T V 2 S V S process transconductance parameter 2) Saturation Region: V S > V GS V T k n W I SAT = VGS V 2 L where k = µ C n ( ) n ox T 2 CUTOFF region: V G < V T Week 9a, Slide 2
Overview of NMOSFET Regions 1. Cutoff region: Conditions: V GS < V T, any value of V S I = 0 2. Linear (or Resistive, or Triode) region: V GS > V T, (V GS V T ) > V S I = (f 1 x f 2 x f 3 )V S where f 1 = µc ox (depends on the fabrication process) f 2 = W/L (chosen by the design engineer) f 3 = f 3 (V GS, V T, V S ) = [V GS V T V S /2] ~ (V GS V T ) if (V GS V T ) >> V S /2 3. Saturation region: V S > (V GS V T ) = V Saturation = (V GS V T ) 2 I = (1/2) f 1 x f 2 x (V GS V T ) 2 Week 9a, Slide 3
MOSFET I vs. V GS Characteristic Typically, V S is fixed when I is plotted as a function of V GS Long-channel MOSFET V S = 2.5 V > V SAT Short-channel MOSFET V S = 2.5 V > V SAT Week 9a, Slide 4
MOSFET V T Measurement V T can be determined by plotting I vs. V GS, using a low value of V S : I (A) I = k n W L V GS V T V 2 S V S 0 V T V GS (V) Week 9a, Slide 5
Subthreshold Conduction (Leakage Current) The transition from the ON state to the OFF state is gradual. This can be seen more clearly when I is plotted on a logarithmic scale: In the subthreshold (V GS < V T ) region, I exp qv nkt GS This is essentially the channelsource pn junction current. (n, the emission factor, is between 1 and 2) (Some electrons diffuse from the source into the channel, if this pn junction is forward biased.) V S > 0 Week 9a, Slide 6
Qualitative Explanation for Subthreshold Leakage The channel V c (at the Si surface) is capacitively coupled to the gate voltage V G : n+ poly-si n+ n+ depletion region EVICE V G W dep p-type Si C dep V = ε W CIRCUIT MOEL Si dep V G C ox C dep + 1 N A V c Week 9a, Slide 7 Using the capacitive voltage divider formula: V c = C ox Cox + C The forward bias on the channel-source pn junction increases with V G scaled by the factor C ox / (C ox +C dep ) Cox + Cdep n = = 1+ C ox dep V G C C dep ox
Slope Factor (or Subthreshold Swing) S S is defined to be the inverse slope of the log (I ) vs. V GS characteristic in the subthreshold region: V S > 0 S n kt q ln(10) Units: Volts per decade 1/S is the slope Note that S 60 mv/dec at room temperature: kt q ln( 10) = 60 mv Week 9a, Slide 8
V T esign Trade-Off (Important consideration for digital-circuit applications) Low V T is desirable for high ON current I SAT (V - V T ) η 1 < η < 2 where V is the power-supply voltage but high V T is needed for low OFF current log I S Low V T I OFF,low VT High V T 0 I OFF,high VT Week 9a, Slide 9 V GS
The MOSFET as a Resistive Switch For digital circuit applications, the MOSFET is either OFF (V GS < V T ) or ON (V GS = V ). Thus, we only need to consider two I vs. V S curves: 1. the curve for V GS < V T 2. the curve for V GS = V I V GS = V (closed switch) R eq V S V GS < V T (open switch) Week 9a, Slide 10
Equivalent Resistance R eq In a digital circuit, an n-channel MOSFET in the ON state is typically used to discharge a capacitor connected to its drain terminal: gate voltage V G = V source voltage V S = 0 V drain voltage V initially at V, discharging toward 0 V I SATn k n = 2 W L ( V V ) 2 Tn C load Week 9a, Slide 11 The value of R eq should be set to the value which gives the correct propagation delay (time required for output to fall to ½V ): R eq 3 4 V I SATn 1 5 6 λ V n
+V dd +V dd = = Figure 0.1 CMOS circuits and their schematic symbols Week 9a, Slide 12
Typical MOSFET Parameter Values For a given MOSFET fabrication process technology, the following parameters are known: V T (~0.5 V) C ox and k (<0.001 A/V 2 ) V SAT ( 1 V) λ ( 0.1 V -1 ) Example R eq values for 0.25 µm technology (W = L): How can R eq be decreased? Week 9a, Slide 13
P-Channel MOSFET Example In a digital circuit, a p-channel MOSFET in the ON state is typically used to charge a capacitor connected to its drain terminal: gate voltage V G = 0 V source voltage V S = V (power-supply voltage) drain voltage V initially at 0 V, charging toward V V 0 V R eq 3 4 I V SATp 1 5 6 λ V p C load I SAT i ( ) 2 k p = 2 W L V V Tp Week 9a, Slide 14
Common-Source (CS) Amplifier The input voltage v s causes v GS to vary with time, which in turn causes i to vary. R V i The changing voltage drop across R causes an amplified (and inverted) version of the input signal to appear at the drain terminal. v s + + + v OUT = v S V BIAS + v IN = v GS Week 9a, Slide 15
Notation Subscript convention: V S V V S, V GS V G V S, etc. ouble-subscripts denote C sources: V, V CC, I SS, etc. To distinguish between C and incremental components of an electrical quantity, the following convention is used: C quantity: upper-case letter with upper-case subscript I, V S, etc. Incremental quantity: lower-case letter with lower-case subscript i d, v ds, etc. Total (C + incremental) quantity: lower-case letter with upper-case subscript i, v S, etc. Week 9a, Slide 16
Load-Line Analysis of CS Amplifier The operating point of the circuit can be determined by finding the intersection of the appropriate MOSFET i vs. v S characteristic and the load line: i (ma) v GS (V) load-line equation: V = R i + v S v S (V) Week 9a, Slide 17
Voltage Transfer Function v OUT v IN Goal: Operate the amplifier in the high-gain region, so that small changes in v IN result in large changes in v OUT (1): transistor biased in cutoff region (2): v IN > V T ; transistor biased in saturation region (3): transistor biased in saturation region (4): transistor biased in resistive or triode region Week 9a, Slide 18
Quiescent Operating Point The operating point of the amplifier for zero input signal (v s = 0) is often referred to as the quiescent operating point. (Another word: bias.) The bias point should be chosen so that the output voltage is approximately centered between V and 0 V. v s varies the input voltage around the input bias point. Note: The relationship between v OUT and v IN is not linear; this can result in a distorted output voltage signal. If the input signal amplitude is very small, however, we can have amplification with negligible distortion. Week 9a, Slide 19
Bias Circuit Example V R 1 R R 2 Week 9a, Slide 20
Rules for Small-Signal Analysis A C supply voltage source acts as a short circuit Even if AC current flows through the C voltage source, the AC voltage across it is zero. A C supply current source acts as an open circuit Even if AC voltage is applied across the current source, the AC current through it is zero. Week 9a, Slide 21
NMOSFET Small-Signal Model G + i d + v gs g m v gs r o v ds S i d g g m o = i v GS i v i v GS S v gs + W L λi i v k S v ( V V ) GS ds = Week 9a, Slide 22 g T m v gs + g o v ds output conductance S transconductance
Channel-Length Modulation If L is small, the effect of L to reduce the inversion-layer resistor length is significant I increases noticeably with L (i.e. with V S ) I I = I (1 + λv S ) λ is the slope I is the intercept V S Week 9a, Slide 23
Small-Signal Equivalent Circuit G + + + v in R 1 R 2 v gs g m v gs r o R v out S S voltage gain v A out v = g = v v out in m v gs = g Week 9a, Slide 24 ( r R ) o m ( r R ) o