Power MOSFET 6 V, 16 m, 61 A, Single P Channel Features Low R DS(on) to Minimize Conduction Losses High Current Capability Avalanche Energy Specified AEC Q11 Qualified These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise noted) Parameter Symbol Value Unit Drain to Source Voltage V DSS 6 V Gate to Source Voltage V GS 2 V Continuous Drain Current R JC (Note 1) Power Dissipation R JC (Note 1) Continuous Drain Current R JA (Notes 1 & 2) Power Dissipation R JA (Notes 1 & 2) Steady State Steady State T C = 25 C I D 61 A T C = 1 C 3 T C = 25 C P D 118 W T C = 1 C 59 T A = 25 C I D 11 A T A = 1 C 8 T A = 25 C P D.1 W T A = 1 C 2.1 Pulsed Drain Current T A = 25 C, t p = 1 s I DM 19 A Current Limited by Package (Note 3) T A = 25 C I Dmaxpkg 6 A Operating Junction and Storage Temperature T J, T stg 55 to 175 Source Current (Body Diode) I S 118 A Single Pulse Drain to Source Avalanche Energy (, V DD = 5 V, V GS = 1 V, I L(pk) = A, L =.3 mh, R G = 25 ) Lead Temperature for Soldering Purposes (1/8 from case for 1 s) C E AS 2 mj T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction to Case Steady State (Drain) R JC 1.3 C/W Junction to Ambient Steady State (Note 2) R JA 37 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface mounted on FR board using a 65 mm 2, 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. V (BR)DSS 6 V G R DS(on) 16 m @ 1 V 22 m @.5 V S 1 2 3 D DPAK CASE 369C STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENT Y WW 5117L G Drain YWW 51 17LG 2 1 Drain 3 Gate Source = Year = Work Week = Device Code = Pb Free Package I D 61 A P Channel Device Package Shipping NVD5117PLTG ORDERING INFORMATION DPAK (Pb Free) 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. Semiconductor Components Industries, LLC, 211 September, 211 Rev. 1 Publication Order Number: NVD5117PL/D
ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = 25 A 6 V Zero Gate Voltage Drain Current I DSS VGS = V, V DS = 6 V 1. A T J = 125 C Gate to Source Leakage Current I GSS V DS = V, V GS = 2 V 1 na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = 25 A 1.5 2.5 V Drain to Source On Resistance R DS(on) V GS = 1 V, 12 16 m 1 V GS =.5 V, 16 22 Froward Transconductance g FS V DS = 15 V, I D = 15 A 3 S CHARGES AND CAPACITANCES Input Capacitance C iss V GS = V, f = 1. MHz, 8 pf Output Capacitance C oss V DS = 25 V 8 Reverse Transfer Capacitance C rss 32 Total Gate Charge Q G(TOT) VDS = 8 V, Threshold Gate Charge Q G(TH) V GS =.5 V 9 nc V GS = 1 V 85 Gate to Source Charge Q GS V GS =.5 V, V DS = 8 V, 13 Gate to Drain Charge Q GD 28 Plateau Voltage V GP 3.2 V SWITCHING CHARACTERISTICS (Notes ) Turn On Delay Time t d(on) Rise Time t r V GS =.5 V, V DS = 8 V, 195 Turn Off Delay Time t d(off), R G = 2.5 5 Fall Time t f 132 DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S = 29 A Reverse Recovery Time t RR 3 22 ns.86 1. V T J = 125 C.7 Charge Time t a V GS = V, dl s /dt = 1 A/ s, 19 Discharge Time t b I s = 29 A 17 36 ns Reverse Recovery Charge Q RR nc. Pulse Test: Pulse Width 3 s, Duty Cycle 2%. 2
TYPICAL CHARACTERISTICS 12 1 8 6 2 V GS = 1 V.5 V.2 V 1 2 3 5 Figure 1. On Region Characteristics V 3.8 V 3.6 V 3. V 3.2 V 3 V 12 1 8 6 2 V DS 1 V T J = 125 C T J = 55 C 2 3 5 6 V GS, GATE TO SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED).65.55.5.35.25.15 2. 1.8 1.6 1. 1.2 1..8 V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On Resistance vs. Gate to Source Voltage V GS = 1 V.5 3 5 6 7 8 9 1.6 5 25 25 5 75 1 125 15 175 T J, JUNCTION TEMPERATURE ( C) Figure 5. On Resistance Variation with Temperature R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I DSS, LEAKAGE (na).2.22.2.18.16.1.12 V GS =.5 V V GS = 1 V.1 1 2 3 5 6 7 8 9 1 11 12 1 1 1 Figure. On Resistance vs. Drain Current and Gate Voltage V GS = V T J = 15 C T J = 125 C 1 5 1 15 2 25 3 35 5 5 55 6 Figure 6. Drain to Source Leakage Current vs. Voltage 3
TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) 6 55 5 5 35 3 25 2 15 C iss V GS = V 1 C 5 oss C rss 1 2 3 5 6 V GS, GATE TO SOURCE VOLTAGE (V) 1 8 6 Q gs Q gd Q T 2 V DS = 8 V 1 2 3 5 6 7 8 9 t, TIME (ns) 1. 1. 1. Figure 7. Capacitance Variation t r t f t d(off) t d(on) V DD = 8 V V GS = 1 V 1. 1 1 1 R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance I S, SOURCE CURRENT (A) 12 1 8 6 2 Q g, TOTAL GATE CHARGE (nc) Figure 8. Gate to Source vs. Total Charge V GS = V..5.6.7.8.9 1. 1.1 1.2 V SD, SOURCE TO DRAIN VOLTAGE (V) Figure 1. Diode Forward Voltage vs. Current 1 1 1 1 V GS = 1 V Single Pulse T C = 25 C 1 s 1 ms 1 ms 1 s R DS(on) Limit Thermal Limit Package Limit.1.1 1 1 1 Figure 11. Maximum Rated Forward Biased Safe Operating Area dc E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 25 2 15 1 5 I D = A 25 5 75 1 125 15 175 T J, STARTING JUNCTION TEMPERATURE ( C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
TYPICAL CHARACTERISTICS R JC(t) ( C/W) EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 1.1 Duty Cycle =.5.2.1.5.2.1 Single Pulse.1.1.1.1.1.1.1 PULSE TIME (sec) Figure 13. Thermal Response 5
PACKAGE DIMENSIONS L3 L b2 e E b3 1 2 3 b A D B DETAIL A c.5 (.13) M C A DPAK (SINGLE GAUGE) CASE 369C 1 ISSUE D C c2 H L2 GAUGE PLANE L L1 DETAIL A ROTATED 9 CW A1 H C SOLDERING FOOTPRINT* Z SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M, 199. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.6 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.86.9 2.18 2.38 A1..5..13 b.25.35.63.89 b2.3.5.76 1.1 b3.18.215.57 5.6 c.18.2.6.61 c2.18.2.6.61 D.235.25 5.97 6.22 E.25.265 6.35 6.73 e.9 BSC 2.29 BSC H.37.1 9. 1.1 L.55.7 1. 1.78 L1.18 REF 2.7 REF L2.2 BSC.51 BSC L3.35.5.89 1.27 L. 1.1 Z.155 3.93 6.2.2 2.58.12 3..118 5.8.228 1.6.63 6.17.23 SCALE 3:1 mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: 33 675 2175 or 8 3 386 Toll Free USA/Canada Fax: 33 675 2176 or 8 3 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 21 33 79 291 Japan Customer Focus Center Phone: 81 3 5773 385 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NVD5117PL/D