FAN73932 Half-Bridge Gate Drive IC Features Floating Channel for Bootstrap Operation to +600V Typically 2.5A/2.5A Sourcing/Sinking Current Driving Capability Extended Allowable Negative V S Swing to -9.8V for Signal Propagation at V BS =15V High-Side Output in Phase of IN Input Signal 3.3V and 5V Input Logic Compatible Matched Propagation Delay for Both Channels Built-in Shutdown Function Built-in UVLO Functions for Both Channels Built-in Common-Mode dv/dt Noise Canceling Circuit Internal 400ns Minimum Dead-Time Description February 2010 The FAN73932 is a half-bridge, gate-drive IC with shutdown and dead-time functions which can drive highspeed MOSFETs and IGBTs that operate up to +600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8V (typical) for V BS =15V. The UVLO circuit prevents malfunction when V DD and V BS are lower than the specified threshold voltage. Applications High-Speed Power MOSFET and IGBT Gate Driver Induction Heating High-Power DC-DC Converter Synchronous Step-Down Converter Motor Drive Inverter The high-current and low-output voltage drop feature makes this device suitable for all kinds of half- and fullbridge inverters, like motor drive inverter, switching mode power supply, induction heating, and high-power DC-DC converter applications. 8-SOP Ordering Information Part Number FAN73932M FAN73932MX Package Operating Temperature Range Eco Status Packing Method 8-SOP -40 C to +125 C RoHS Tube Tape & Reel For Fairchild s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Typical Application Diagrams +15V Up to 600V PWM IC PWM Control Shutdown 1 IN 2 SD 3 COM 4 LO V B HO V S V DD 8 7 CBOOT DBOOT 6 RBOOT 5 +15V Load Figure 1. Typical Application Circuit Internal Block Diagram 8 V B UVLO IN 1 200K SCHMITT TRIGGER INPUT HS(ON/OFF) PULSE GENERATOR NOISE CANCELLER R R S Q DRIVER 7 6 HO V S 5V SHOOT THOUGH PREVENTION UVLO 5 V DD SD 2 DEAD-TIME { 400ns } LS(ON/OFF) DELAY DRIVER 4 LO 3 COM Figure 2. Functional Block Diagram
Pin Configuration IN 1 SD 2 COM 3 LO 4 FAN73932 8 V B 7 HO 6 V S 5 V DD Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 IN Logic Input for High-Side and Low-Side Gate Driver Output, In-Phase with HO 2 SD Logic Input for Shutdown 3 COM Ground 4 LO Low-Side Driver Return 5 V DD Supply Voltage 6 V S High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 V B High-Side Floating Supply
Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C unless otherwise specified. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage -0.3 625.0 V V S High-Side Floating Offset Voltage V B -25.0 V B +0.3 V V HO High-Side Floating Output Voltage V S -0.3 V B +0.3 V V LO Low-Side Output Voltage -0.3 V DD +0.3 V V DD Low-Side and Logic Fixed Supply Voltage -0.3 25.0 V V IN Logic Input Voltage (IN) -0.3 V DD +0.3 V V SD Logic Input Voltage (SD) -0.3 5.5 V COM Logic Ground and Low-Side Driver Return V DD -25.0 V DD +0.3 V dv S /dt Allowable Offset Voltage Slew Rate ± 50 V/ns P D Power Dissipation (1, 2, 3) 0.625 W θ JA Thermal Resistance 200 C/W T J Junction Temperature +150 C T STG Storage Temperature -55 +150 C Notes: 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed P D under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V S +10 V S +20 V V S High-Side Floating Supply Offset Voltage 6-V DD 600 V V HO High-Side Output Voltage V S V B V V DD Low-Side and Logic Fixed Supply Voltage 10 20 V V LO Low-Side Output Voltage COM V DD V V IN Logic Input Voltage (IN) COM V DD V V SD Logic Input Voltage (SD) (4) COM 5 V T A Operating Ambient Temperature -40 +125 C Note: 4. Shutdown (SD) input is internally clamped with 5.2V.
Electrical Characteristics V BIAS (V DD, V BS )=15.0V, COM=0V, and T A = 25 C, unless otherwise specified. The V IN and I IN parameters are referenced to COM and are applicable to the respective input leads: IN and SD. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Parameter Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION I QDD Quiescent V DD Supply Current V IN =0V, SD=5V 320 700 μa I QBS Quiescent V BS Supply Current V IN =0V or 5V, SD=5V 50 120 μa I PDD Operating V DD Supply Current f IN =20KHz, No Load, SD=5V 700 1300 μa I PBS Operating V BS Supply Current C L =1nF, f IN =20KHz, rms, SD=5V 420 800 μa I SD Shutdown mode Supply Current SD=0V, SD=5V 400 800 µa I LK Offset Supply Leakage Current V B =V S =600V 10 μa BOOTSTRAPPED SUPPLY SECTION V DDUV+ V BSUV+ V DDUV- V BSUV- V DDUVH- V BSUVH V DD and V BS Supply Under-Voltage Positive Going Threshold Voltage V DD and V BS Supply Under-Voltage Negative Going Threshold Voltage V DD and V BS Supply Under-Voltage Lockout Hysteresis Voltage V DD =V BS =Sweep 8 9 10 V V DD =V BS =Sweep 7.4 8.4 9.4 V V DD =V BS =Sweep 0.6 V INPUT LOGIC SECTION V IH Logic 1 Input Voltage for HO & Logic 0 for LO 2.5 V V IL Logic 0 Input Voltage for HO & Logic 1 for LO 0.8 V I IN+ Logic Input High Bias Current V IN =5V, SD=0V 25 60 μa I IN- Logic Input Low Bias Current V IN =0V, SD=5V 3 μa R IN Logic Input Pull-Down Resistance 200 KΩ V SDCLAMP Shutdown (SD) Input Clamping Voltage 5.0 5.5 V SD+ Shutdown (SD) input Positive-Going Threshold 2.5 V SD- Shutdown (SD) input Negative-Going Threshold 0.8 V R PSD Shutdown (SD) Input Pull-Up Resistance 200 KΩ GATE DRIVER OUTPUT SECTION V OH High-level Output Voltage (V BIAS - V O ) No Load 1.5 V V OL Low-level Output Voltage No Load 100 mv I O+ Output High, Short-Circuit Pulsed Current (5) V HO =0V, V IN =5V, PW 10µs 2.0 2.5 A I O- Output Low, Short-Circuit Pulsed Current (5) V HO =15V,V IN =0V, PW 10µs Allowable Negative V V S Pin Voltage for IN Signal S Propagation to HO Note: 5 These parameters guaranteed by design. 2.0 2.5 A -9.8-7.0 V
Dynamic Electrical Characteristics V BIAS (V DD, V BS )=15.0V, COM=0V, C L =1000pF, and T A =25 C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit t ON Turn-On Propagation Delay Time (6) V S =0V 600 850 ns t OFF Turn-Off Propagation Delay Time V S =0V 200 350 ns t SD Shutdown Propagation Delay Time 140 220 ns Mt ON Delay Matching, HO and LO Turn-On 0 50 ns Mt OFF Delay Matching, HO and LO Turn-Off 0 50 ns t R Turn-On Rise Time V S =0V 25 50 ns t F Turn-Off Fall Time V S =0V 20 35 ns DT Dead-Time: LO Turn-Off to HO Turn-On and HO Turn-Off to LO Turn-On 300 400 500 ns MDT Dead-time matching= DT LO-HO - DT HO-LO 0 50 ns Note: 6. The turn-on propagation delay time included dead-time.
Typical Characteristics t ON [ns] 800 750 700 650 600 550 500 450 400 Figure 4. Turn-On Propagation Delay t OFF [ns] 280 240 200 160 120 80 40 Figure 5. Turn-Off Propagation Delay 50 30 40 20 t R [ns] 30 t F [ns] 10 20 10 0 0-10 Figure 6. Turn-On Rise Time Figure 7. Turn-Off Fall Time 30 30 20 20 MT ON [ns] 10 0 MT OFF [ns] 10 0-10 -10-20 -20 Figure 8. Turn-On Delay Matching Figure 9. Turn-Off Delay Matching 7
Typical Characteristics (Continued) DT [ns] 550 500 450 400 350 300 Figure 10. Dead-Time t SD [ns] 300 250 200 150 100 50 Figure 11. Shutdown Propagation Delay 400 120 100 I QDD [μa] 350 300 I QBS [μa] 80 60 40 20 250 0 Figure 12. Quiescent V DD Supply Current Figure 13. Quiescent V BS Supply Current 1200 1000 1000 800 I PDD [μa] 800 600 I PBS [μa] 600 400 400 200 200 0 Figure 14. Operating V DD Supply Current Figure 15. Operating V BS Supply Current 8
Typical Characteristics (Continued) V DDUV+ 10.0 9.5 9.0 8.5 8.0 Figure 16. V DD UVLO+ V DDUV- 9.5 9.0 8.5 8.0 7.5 Figure 17. V DD UVLO- 10.5 10.0 10.0 9.5 V BSUV+ 9.5 9.0 V BSUV- 9.0 8.5 8.0 8.5 7.5 8.0 7.0 Figure 18. V BS UVLO+ Figure 19. V BS UVLO- V OH 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 V OL 1.0 0.8 0.6 0.4 0.2 0.0-0.2-0.4 Figure 20. High-Level Output Voltage Figure 21. Low-Level Output Voltage 9
Typical Characteristics (Continued) V IH 3.0 2.5 2.0 1.5 1.0 Figure 22. Logic High Input Voltage V IL 3.0 2.5 2.0 1.5 1.0 0.5 Figure 23. Logic Low Input Voltage 50-8 40-9 I IN+ [μa] 30 20 V S -10-11 10-12 0-13 Figure 24. Logic Input High Bias Current Figure 25. Allowable Negative V S Voltage. 10
Switching Time Definitions SD LO 1 IN V B 8 2 SD HO 7 10uF 100nF 1nF 3 COM V S 6 4 LO V DD 5 1nF 10uF 100nF Figure 26. Switching Time Test Circuit +15V HO +15V IN HO LO SD DT1 DT2 DT1 DT2 Shutdown DT2 DT1 Shutdown DT1 DT2 Figure 27. Input/Output Timing Diagram IN 50% 50% t OFF t R t ON t R LO 10% 10% t ON t R HO 10% t OFF t F 10% Figure 28. Switching Time Waveform Definition
50% SD HO or LO Figure 29. Shutdown Waveform Definition IN 50% 50% t SD t OFF DT HO-LO LO 10% DT LO-HO HO 10% t OFF MDT= DT LO-HO - DT HO-LO Figure 30. Dead-Time Waveform Definition IN(LO) 50% 50% 50% 50% IN(HO) MT off MT on LO HO 10% 10% Figure 31. Delay Matching Waveform Definition
Mechanical Dimensions 6.20 5.80 PIN ONE INDICATOR (0.33) 8 1 5.00 4.80 3.81 4 1.27 5 A B 4.00 3.80 0.25 M C BA 0.65 1.75 5.60 1.27 LAND PATTERN RECOMMENDATION 1.75 MAX R0.10 R0.10 0.25 0.10 8 0 0.90 0.406 (1.04) DETAIL A SCALE: 2:1 C 0.51 0.33 0.50 x 45 0.25 SEATING PLANE 0.10 C GAGE PLANE 0.36 SEE DETAIL A OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE 0.25 0.19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 Figure 32. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
FAN73932 Rev. 1.0.1 14
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