PLL EXERCISE Φ in (S) PHASE DETECTOR + Kd - V d (S) R1 R2 C2 220k 10k 10 nf Φ o (S) VCO Kv S V c (S) R3 16k C3 1 nf V dem (S) VCO Characteristics Phase Detector Characteristics V d ave F o 150k +5V (H z) 50k 0V 5V V c 2π π 0 π 2π Φ e (rad) A) Determine K v in Hz/V and r/s/v, the VCO center frequency and the PLL lock range. B) Determine the phase detector sensitivity. From the phase detector characteristics, explain why the PLL unlocks when it exceeds the phase error limits. -1-
C) Using Mason's rule, determine the following transfer functions and state what type of frequency response the TF's exhibit? Φ o (S) Φ in (S) and V dem (S) ω in (S) = V dem (S) S Φ in (S ) D) From the above TF's, calculate the numerical values of ζ and ω n. E) Using System View with file PLL-Tcap-ASS3, run the simulation and observe V dem to determine the capture time, or acquisition time, for constant input frequencies of 105 khz and 110 khz - one frequency at a time. Also measure the period of the first two -ve peaks of V dem - how is it related to the input frequency and the VCO frequency? Also observe the instantaneous VCO frequency and measure F o ave and F o of the settled waveform. F o is caused by the large ripple voltage present at the VCO input which the lag-lead filter is very poor at filtering down. This HF ripple component is undesirable as it frequency modulates the VCO and introduces spurious FM sidetones in the frequency spectrum. Observe the V C waveform and meassure its average and p-p value as well as the HF ripple frequency. Verify that V C (pp) = 5 * 10K / (10K+220k) and F o (pp) = V C (pp) * K v. The PLL shown below uses an "in-loop" ripple filter in order to reduce the ripple on V C thereby reducing the spurious FM sidebands at the VCO O/P. Use file PLL-Tcap-ASS3B to simulate it and repeat all of the above steps of part E. Φ in (S) PHASE DETECTOR V d (S) + - K d LAG-LEAD FILTER 220k 10k 10 nf RIPPLE FILTER 220k 27 pf 220k 27 pf Φ o (S) VCO Kv S V c (S) = V dem (S) -2-
F) Using System View with file PLL-Fcap-ASS4, run the simulation and observe ω in, ω o and V dem to determine the capture range of the PLL by ramping the input frequency up from 75 khz at a rate of 10 khz/s and also by ramping the input frequency down from 125 khz at a rate of -10 khz/s. NOTE: If the input frequency is ramped too fast the results will be different and PLL may not even capture the input signal. Repeat the above measurements of part F with file PLL-Fcap-ASS4B which simulates the above PLL with the "in-loop" ripple filter. NOTE: The in-loop ripple filter makes the PLL a fourth-order PLL and care must be exercised in choosing its time constant as it could render the PLL very unstable by lowering the damping factor. As a rule, make 0,382/τ 3 > 10*ω n and R 3 >> R 2 of lag-lead filter; here τ 3 = 220K * 27 pf and ω n is the value found for the second-order loop without the in-loop ripple filter. For the purpose of determining the new PLL TF use the following approximate filter TF where it is assumed that the ripple filter does not load the output of the lag-lead filter. F(S) ( 1+ Sτ 2 ) ( 1+ S( τ 1 +τ 2 ) 1 ( S 2 τ 2 3 + 3 S τ 3 +1) G) FM Demodulation i) If the input is an FM signal as defined below, determine the peak to peak values of the phase error and V dem, and the average phase error. Replace S with jω mod in TF's found in step C to find answers. FM input specifications: Case#1: Case#2: Case#3: Case#4: F car = 100 khz, 1 khz peak carrier frequency deviation, sinusoidal modulation, F mod = 50 Hz F car = 100 khz, 1 khz peak carrier frequency deviation, sinusoidal modulation, F mod = 1 khz F car = 100 khz, 3,01 khz peak carrier frequency deviation, sinusoidal modulation, F mod = 1 khz Label regions of +ve and -ve feedback on φ e waveform and explain why the PLL unlocks. F car = 100 khz, 3,05 khz peak carrier frequency deviation, sinusoidal modulation, F mod = 1 khz Label regions of +ve and -ve feedback on φ e waveform and explain why the PLL unlocks. -3-
ii) Use System View file PLLFMDEM-ASS2 to simulate and verify your answers. iii) Using System View, determine the frequency spectrum of the input signal of case #2. What is the spacing between adjacent sidetones? What is the approximate BW of the spectrum? Does it verify Carson's rule BW 2( F+F mod )? iv) What modulation frequency produces the maximum phase error? Verify with System View using F car = 100 khz and 1 khz peak carrier frequency deviation and then compare to cases #1 and #2. H) What values of R 1, R 2, C 2, R 3 and C 3 should be used in order to obtain a flat (Butterworth) demodulator gain response with a bandwith of 2 khz? I) FSK Demodulator i) If the input is an FSK signal with frequencies of 99 khz and 101 khz and a bit rate of 500 bps, determine the amplitude of V dem and the maximum phase error. ii) Verify the above with System View file PLLFSKDEM-ASS5 and also observe the phase error signal - measure Φ e min, Φ e max, Φ e ave, settled Φ e (pp) and overshoot. Also observe the instantaneous ω in and ω o waveforms and see how they track each other. Notice that ω o has a high ripple content because of the large ripple voltage at the VCO input. iii) If the input is an FSK signal with frequencies of 97,5 khz and 102,5 khz and a bit rate of 500 bps, determine the amplitude of V dem. Verify the above with System View file PLLFSKDEM-ASS5 and also observe the phase error signal. What happens when the phase error goes through π radians? Does it stay locked? Why not? iv) Repeat steps ii and iii above with file PLLFSKDEM-ASS5B which uses the PLL with the in-loop ripple filter. According to the results has the PLL damping factor gone up or down? Explain. -4-
FILE: PLLFMDEM-ASS1-5-
FILE: PLLFMDEM-ASS2-6-
FILE: PLL-Tcap-ASS3-7-
FILE: PLL-Tcap-ASS3B -8-
FILE: PLL-Fcap-ASS4-9-
FILE: PLL-Fcap-ASS4B -10-
FILE: PLLFSKDEM-ASS5-11-
FILE: PLLFSKDEM-ASS5B -12-