LECTURE 4 SPICE MODELING OF MOSFETS Objectives for Lecture 4* Understanding the element description for MOSFETs Understand the meaning and significance of the various parameters in SPICE model levels 1 through 3 for MOSFETS Understand the basic capacitance models Have a general notion of BSIM model parameters Become award of some newer models Understand the use and shortcomings of the models covered Assignment Kang and Leblebici pp. 117-139 and Digital Circuit Simulation Using Star-HSpice * *Lecture length - 105 minutes 1 1/7/98 1/11/01 THE MOSFET DESCRIPTION LINES Model and Element References Massobrio, G., and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd Edition, McGraw-Hill, 1993. Foty, D., MOSFET Modeling with SPICE Principles and Practice, Prentice Hall PTR, 1997. HSPICE Manual, Chapter 15 MOSFET Introduction, Avant!, 1996. What does SPICE stand for? Simulation Program with Integrated Circuit Emphasis The MOSFET Model and Element Description Lines Process and circuit parameters which apply to a particular class of MOSFETS with varying dimensions are described for that class of MOSFETs in a single.model line in which + is used to denote line continuation. 2 1/7/98 1/11/01
Element Line (Continued) The dimensions are given on the element description line. In both, it is critical to watch the units; they are basically illogical! The SPICE element description line for a MOSFET has the following form: Mxxxxxxx nd ng ns <nb> mname < L=val W=val AD=val AS=val PD=val + PS=val NRD=val NRS=val OFF IC=vds, vgs, vbs TEMP=val> All parameter value pairs between < and > are optional. Additional optional HSPICE parameters: < RDC=val RSC=val M=val DTEMP=val GEO=val DELVTO=val > TEMP=val is not used on element line in HSPICE and not used for level 4 or 5 (BSIM) models. Parameter Definitions: (Obsolete) cd /afs/engr.wisc.edu/apps/ hspice.1997.2/97/docs/hspice/publish; open mosfet_introduction.man with viewer. Go to page 8. 3 1/7/98 1/11/01 Level 1 (Shichman-Hodges) DC Model Equations V T Equation as derived previously. I D Equations as derived previously with linear mode equation times ( 1 + λv DS ) for continuity across linear-saturation boundary. Both use L eff in place of L where: L eff = L 2 LD Key Parameters: What do they represent? See Kang and Leblebici Table 4.1 NMOS, PMOS (obvious) MOSFET channel type KP process transconductance k VTO (note O, not 0) zero substrate-bias threshold voltage V T0 GAMMA substrate-bias or body-effect coefficient γ PHI twice the Fermi potential 2φ F LAMBDA channel length modulation λ 4 1/7/98 1/11/01
Level 1 (Continued) Additional Parameters: What do they represent? LD Lateral diffusion (If not present, may need to find L eff manually!) TPG Type of gate material: 0 Al, +1 opposite to substrate, 1 same as substrate. Default is +1. For the typical CMOS process, TPG = 1 for NMOS and 1 for PMOS. NSUB substrate impurity concentration N A, N D NSS Surface state density Used to define surface component of V T0. TOX Oxide Thickness t ox U0 (note 0, not O) Surface mobility µ 0 RD, RS Drain Resistance, Source Resistance RSH Drain and Source Sheet Resistance (Ω/ ) Derived Parameters. Note that if some parameters missing, others, if present, can be used to derive them. E. g., NSUB to derive PHI, and TOX and U0 to derive KP. Question: What parameters to derive GAMMA? If the derivable parameters are present in the model, they will be used; if not, derived if possible from other parameters (and defaults), else, defaulted. 5 1/7/98 1/11/01 Level 2 What about defaults and units? See Table 4.1. of Kang and Leblebici Other parameters in Level 1 are related to capacitance (later) or irrelevant to digital applications. Level 2 Analytical model that takes into account small geometry effects. Equations that use most of the parameters are given in the text. Parameters in addition to those for Level 1: 6 1/7/98 1/11/01 NFS Fast surface state density Used in modeling subthreshold conduction. NEFF Total channel charge coefficient Empirical fitting factor multiplied times NSUB in the calculation of the short channel effect on γ. Used only in Level 2. XJ Junction depth of source and drain. VMAX Maximum drift velocity for carriers used for modeling velocity saturation. DELTA Channel width effect on V T.
Level 2 (Continued) XQC Coefficient of channel charge share. Used to specify the portion of the channel charge attributed to the drain. Also, more importantly causes the Ward capacitive model to replace the Meyer capacitance model. Both have their disadvantages. Next three parameters produce a multiplicative surface mobility degradation factor to multiply times KP and appear in Level 2 only. UCRIT Critical electric field for mobility degradation. UEXP Exponent coefficient for mobility degradation. UTRA Transverse field coefficient for mobility degradation. Coefficient of V DS in denominator of the factor. See Table 4.1. of Kang and Leblebici 7 1/7/98 1/11/01 Level 3 More empirical and less analytical than Level 2; this permits improved convergence and simpler computations while sacrificing little accuracy. The parameters it has beyond those in Level 2 (Note that the following Level 2 parameters are deleted: NEFF, UCRIT, UEXP, and UTRA.) KAPPA Saturation field factor. An empirical factor in the equation for the channel length in saturation ETA Static feedback on V T. Models effect of V DS on V T, i. e., DIBL (Drain-Induced Barrier Lowering) THETA Mobility modulation. Models the effect of V GS on surface mobility See Table 4.1. of Kang and Leblebici 8 1/7/98 1/11/01
CAPACITANCE MODELS Levels 1 through 3 use the Meyer capacitance model (see Kang and Leblebici Fig. 3.32) as the default for the channel capacitance with the option of the Ward model (see Kang and Leblebici Fig. 4.8) in Levels 2 and 3. For the source and drain capacitances, note the junction diode equation with reverse bias V with V T, the thermal voltage, I = V V T I S e 1 = I s for V 4V T and recall that: C j = C j0 -------------------------------- ( 1 V φ 0 ) m where m = 1/2 for an abrupt junction and m = 1/3 for a graded junction. The parameters: IS Bulk junction saturation current. JS Bulk junction saturation current density (used with junction areas) 9 1/7/98 1/11/01 CAPACITANCE MODELS (Continued) PB φ 0 Bulk junction Potential (Built-in voltage) CJ Zero-bias bulk junction capacitance per m 2 MJ m Bulk junction grading coefficient CJSW Zero-bias perimeter capacitance per m MJSW m Perimeter capacitance grading coefficient FC Bulk junction forward bias coefficient - used in evaluating capacitance under strong forward bias. CGBO Gate-bulk overlap capacitance per meter of L; should be set to 0 if modeled as interconnect instead. CGDO Gate-drain overlap capacitance per meter of W GDSO Gate-source overlap capacitance per meter of W See Table 4.1. of Kang and Leblebici See scn06hp.l3 model (Obsolete). 10 1/7/98 1/11/01
MORE SPICE MODELS BSIM (LEVEL 4) An empirical model that includes: all of the typical small geometry effects the nonuniform doping profile for ion-implanted devices an automatic parameter extraction program which produces a consistent set of parameters L and W for the channel For BSIM parameters, see Foty Table 8.1 We will not look at these parameters in detail, but it is quite important to look at the form of the electrical parameters. Each electrical parameter P is represented by three process parameters P 0, P L, and P W associated with P: P P ----------------------------- L ----------------------------- W P = P L DL W DW 0 + + L eff W eff 11 1/7/98 1/11/01 MORE SPICE MODELS BSIM (Continued) L and W are drawn dimensions and DL and DW are the net size changes in the drawn dimensions due to the entire sequence of fabrication steps. The differences shown give L eff and W eff. The equation for P allows for an adjustment of the electrical parameter as a function of the effective length and width of the channel. Parameter extraction uses devices of several sizes. P 0 is for long, wide MOS- FET. BSIM also uses a new approach to capacitance modeling that avoids the difficulties of errors and lack of charge conservation in the Meyer model and the errors and convergence problems in the Ward model. See Massobrio and Antognetti p. 219 for trios of parameters. Note that model file scn06hp.l13 has only numerical values identified by position; this is an alternate form of the model. 12 1/7/98 1/11/01
MORE SPICE MODELS HSPICE Level 28, BSIM2, BIM3 HSPICE Level 13 is BSIM HSPICE Level 28 a very popular modification of BSIM, but can only be used in HSPICE BSIM2 (HSPICE Level 39) typical model today for those not using HSPICE BSIM3 Version 3 (HSPICE Level 49) a complex new public domain model that is frequently used today. 13 1/7/98 1/11/01 WHICH MODEL SHOULD I USE? Level 1: At best, for quick estimates not requiring accuracy. Very poor for small geometry devices. Viewed as obsolete by some. Level 2: Due to convergence problems and slow computation rate, abandoned in favor of Level 3 or higher. Level 3: Good for MOSFETs down to about 2 microns. BSIM Level 4 (HSPICE Level 13): Good for small geometry MOSFETS with L down to 1 micron and t ox down to 150 Angstroms. Problems near V sat ; negative output conductance; discontinuity in current at V T. For submicron dimensions, replaced by BSIM2 and HSPICE Level 28. BSIM2 (HSPICE Level 39): Good for small geometry MOSFETs with L down to 0.2 micron and t ox down to 36 Angstroms. HSPICE Level 28: BSIM with its problems solved; good choice for HSPICE users. BSIM3 Version 3 (HSPICE Level 49): Most accurate, but complex. 14 1/7/98 1/11/01
SUMMARY Learned the element description line for a MOSFET Reviewed the first generation SPICE model parameters, levels 1, 2, and 3 Reviewed the device capacitances and associated parameters Obtained a sense of the form of the parameters for the BSIM model Obtained an awareness of some of the newer models Obtained a comparative viewpoint of the models and their use. 15 1/7/98 1/11/01