Nikon 12.1 Mp CMOS Image Sensor from a D3s DSLR Camera with NC81361A Die Markings Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package, and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors, Capacitors, and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan-View Analysis 4.3 Pixel Array Cross Section Parallel to Row Select Line 4.4 Pixel Array Cross Section Parallel to Column Out Line 4.5 Color Filters, Lenses, and Dark Pixels 5 Critical Dimensions 5.1 Die and Bond Pad Dimensions 5.2 Dielectric Thicknesses 5.3 Metallization Critical Dimensions 5.4 Via and Contact Dimensions 5.5 MOS Transistor and Poly Dimensions 5.6 LOCOS Isolation 5.7 Well Depths and Die Thickness 5.8 Pixel Horizontal Dimensions 5.9 Pixel Vertical Dimensions
Imager Process Review 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 D3s Camera Front 2.1.2 D3s Camera Back 2.1.3 Camera Module Front 2.1.4 Camera Module Back 2.1.5 Image Sensor Package Front 2.1.6 Image Sensor Package Back 2.1.7 Image Sensor Package X-Ray 2.1.8 NC81361A Die Photograph 2.1.9 NC81361A Die Markings A 2.1.10 NC81361A Die Markings B 2.1.11 NC81361A Filter and Lens Alignment Vernier 2.1.12 Analysis Sites 2.2.1 NC81361A Sensor Tilt View 2.2.2 Die Corner A 2.2.3 Die Corner B 2.2.4 Die Corner C 2.2.5 Die Corner D 2.2.6 Active Pixel Array Corner A 2.2.7 Active Pixel Array Corner C 2.2.8 RGB Color Filter Array 2.2.9 Minimum Pitch Bond Pads 2.2.10 Bond Pad Dimensions 2.2.11 NAND Cell at Poly 3 Process Analysis 3.1.1 General Structure Periphery 3.1.2 Die Thickness 3.1.3 Die Edge 3.1.4 Die Seal 3.2.1 Bond Pad Overview 3.2.2 Bond Pad Edge 3.3.1 Passivation 3.3.2 IMD 2 and IMD 1 3.3.3 PMD 3.4.1 Minimum Pitch Metal 3 3.4.2 Metal 3 and Metal 2 Thicknesses 3.4.3 Metal 3 Barrier/Adhesion Layer TEM 3.4.4 Metal 2 Top TEM 3.4.5 Metal 2 Barrier/Adhesion Layer TEM
Overview 1-2 3.4.6 Minimum Pitch Metal 2 3.4.7 Minimum Pitch Metal 1 Pixel Array 3.4.8 Metal 1 Thickness TEM 3.4.9 Metal 1 Top TEM 3.4.10 Metal 1 Barrier/Adhesion Layer TEM 3.5.1 Minimum Pitch Via 2s 3.5.2 Minimum Pitch Via 1s and Contacts 3.5.3 Via 1 TEM 3.5.4 Contact to Poly 3.5.5 Detail of Contact to Substrate 3.6.1 MOS Transistor Layout 3.6.2 Minimum Gate Length NMOS Transistor Pixel Array 3.6.3 Minimum Gate Length Logic Transistors 3.6.4 Transistor Side Wallspacer TEM 3.6.5 Gate Oxide TEM 3.6.6 MOS Capacitor Plan View 3.6.7 MOS Capacitor SEM 3.7.1 Minimum Width LOCOS 3.7.2 Poly Over LOCOS 3.8.1 Peripheral P-Well 3.8.2 SCM of Pixel Array Well Structure 3.8.3 SRP of Peripheral N-Well 3.8.4 SRP of Peripheral P-Well 1 3.8.5 SRP of Array Wells 4 Pixel Analysis 4.1.1 Pixel Schematic 4.2.1 RGB Bayer Patterned Color Filter Array 4.2.2 Edge of Organic Lens Array Tilt View 4.2.3 Organic Lens Plan View 4.2.4 Nitride Lens Tilt View 4.2.5 Nitride Lens Plan View 4.2.6 Pixel at Metal 3 4.2.7 Pixel at Metal 2 4.2.8 Pixel at Metal 1 4.2.9 Pixel at Poly 4.2.10 Pixel at Diffusion 4.2.11 Bevel SCM of Pixels 4.3.1 Planes of Cross-Sectioning Parallel to Row Select Line 4.3.2 General Pixel Structure Oxide Etch (A) 4.3.3 Transfer Gate (T1) and AR Layer Overview (A) 4.3.4 Dual AR Layers (A) 4.3.5 Green Pixel AR Layer TEM (A)
Overview 1-3 4.3.6 Transfer Gate Length (T1, B) 4.3.7 Reset Gate Length (T2, C) 4.3.8 Source Follower Gate Length (T3, C) 4.3.9 Row Select Gate Length (T4, C) 4.3.10 Transfer Gate Oxide Thickness (B) 4.4.1 Planes of Cross-Sectioning Parallel to Column Out Line 4.4.2 Reset Transistor (T2) Gate Width (Y) 4.4.3 Source Follower Transistor (T3) Gate Width (X) 4.4.4 Row Select Transistor (T4) Gate Width (W) 4.4.5 V SS and Floating Node Contacts (Z) 4.5.1 Organic Lens Overview 4.5.2 Organic Lens Shift 4.5.3 Nitride Lens Shift 4.5.4 Red Color Filter 4.5.5 Green Color Filter 4.5.6 Blue Color Filter 4.5.7 TEM of Red/Green Color Filter Interface 4.5.8 Detail of Nitride Lens Edge 4.5.9 Dark Pixel Overview Bottom Right 4.5.10 Edge of Color Filter and Nitride Lens Array 4.5.11 Start of Dark Pixels 4.5.12 Outer Edge of Organic Layers
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 NC81361A Device Summary 1.6.1 NC81361A Process Summary 2 Device Overview 2.2.1 Die, Bond Pad, and Standard Cell Dimensions 3 Process Analysis 3.3.1 Measured Dielectric Thicknesses 3.4.1 Metallization Thicknesses 3.4.2 Metallization Width and Pitch 3.5.1 Via and Contact Dimensions 3.6.1 Peripheral MOS Transistor, Capacitor, and Poly Dimensions 3.7.1 LOCOS Critical Dimensions 3.8.1 Well Depths and Die Thickness 4 Pixel Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Pixel Transistor Physical Dimensions 5 Critical Dimensions 5.1.1 Die, Bond Pad, and Standard Cell Dimensions 5.2.1 Measured Dielectric Thicknesses 5.3.1 Metallization Thicknesses 5.3.2 Metallization Width and Pitch 5.4.1 Via and Contact Dimensions 5.5.1 Peripheral MOS Transistor, Capacitor, and Poly Dimensions 5.6.1 LOCOS Critical Dimensions 5.7.1 Well Depths and Die Thickness 5.8.1 Pixel Horizontal Dimensions 5.9.1 Pixel Vertical Dimensions 5.9.2 Pixel Transistor Physical Dimensions
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