NTYN1 Preferred Device Power MOSFET 123 A, V NChannel EnhancementMode TO264 Package Features SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Avalanche Energy Specified IDSS and R DS(on) Specified at Elevated Temperature PbFree Package is Available* Applications PWM Motor Control Power Supplies Converters MAXIMUM RATINGS (T C = 25 C unless otherwise noted) Rating Symbol Value Unit DrainSource Voltage V DSS V DrainGate Voltage (R GS = 1 M ) V DGR V GateSource Voltage Continuous NonRepetitive (t p 1 ms) Drain Current (Note 1) Continuous @ T C = 25 C Pulsed Total Power Dissipation (Note 1) Derate above 25 C V GS V GSM 2 4 I D 123 I DM 369 P D 313 2.5 Operating and Storage Temperature Range T J, T stg 55 to 15 Single Pulse DraintoSource Avalanche Energy Starting T J = 25 C (V DD = 8 Vdc, V GS = 1 Vdc, Peak I L = Apk, L =.1 mh, R G = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes,.125 in from case for 1 seconds V V A A Watts W/ C C E AS 5 mj R JC.4 R JA 25 C/W T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 1 s, DutyCycle = 2%. 1 2 3 123 A, V 9 m @ V GS = 1 V (Typ) G NChannel ORDERING INFORMATION Device Package Shipping NTYN1 TO264 25 Units/Rail NTYN1G TO264 CASE 34G STYLE 1 A YY WW G Preferred devices are recommended choices for future use and best overall value. D S MARKING DIAGRAM & PIN ASSIGNMENT NTYN1 AYYWWG = Assembly Location = Year = Work Week = PbFree Package TO264 (PbFree) 1 2 3 G D S 25 Units/Rail *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 26 March, 26 Rev. 2 1 Publication Order Number: NTYN1/D
NTYN1 ELECTRICAL CHARACTERISTICS (T J = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS DrainSource Breakdown Voltage (V GS =, I D = 25 A) (Positive Temperature Coefficient) V (BR)DSS 144 Vdc mv/ C Zero Gate Voltage Drain Current (V GS = Vdc, V DS = Vdc, T J = 25 C) (V GS = Vdc, V DS = Vdc, T J = 15 C) I DSS 1 Adc GateBody Leakage Current (V GS = 2 Vdc, V DS = ) I GSS nadc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (V DS = V GS, I D = 25 Adc) (Negative Temperature Coefficient) Static DrainSource OnState Resistance (V GS = 1 Vdc, I D = 5 Adc) (V GS = 1 Vdc, I D = 5 Adc, 15 C) V GS(th) 2. R DS(on) 3.1 1.6.9.19 4..1.21 DrainSource OnVoltage (V GS = 1 Vdc, I D = Adc) V DS(on).8 1. Vdc Forward Transconductance (V DS = 6 Vdc, I D = 5 Adc) g FS 73 Mhos DYNAMIC CHARACTERISTICS Input Capacitance C iss 7225 111 pf Output Capacitance (V DS = 25 Vdc, V GS = Vdc, f = 1 MHz) C oss 18 254 Reverse Transfer Capacitance C rss 27 54 SWITCHING CHARACTERISTICS (Notes 2, 3) TurnOn Delay Time Rise Time (V DD = 5 Vdc, I D = Adc, t r 15 265 TurnOff Delay Time V GS = 1 Vdc, R G = 9.1 ) t d(off) 34 595 Vdc mv/ C t d(on) 3 55 ns Fall Time t f 25 435 Total Gate Charge Q T 2 35 nc GateSource Charge (V DS = 8 Vdc, I D = Adc, Q 1 4 V GS = 1 Vdc) Q 2 BODYDRAIN DIODE RATINGS (Note 2) Forward OnVoltage (I S = Adc, V GS = Vdc) (I S = Adc, V GS = Vdc, T J = 15 C) Reverse Recovery Time (I S = Adc, V GS = Vdc, di S /dt = A/ s) Q 3 86 V SD 1.2.94 1.1 Vdc t rr 21 ns t a 155 t b 55 Reverse Recovery Stored Charge Q RR 1.8 C 2. Indicates Pulse Test: Pulse Width 3 s max, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperature. 2
NTYN1 2 15 5 V GS = 9. V V GS = 1 V T J = 25 C V GS = 8. V V GS = 7. V V GS = 6. V V GS = 6.5 V V GS = 5.6 V V GS = 5. V V GS = 4.6 V 2 4 6 8 1 V DS, DRAINTOSOURCE VOLTAGE (V) Figure 1. OnRegion Characteristics 2 V DS 1 V 15 5 T J = C T J = 25 C T J = 55 C 2 4 6 8 1 V GS, GATETOSOURCE VOLTAGE (V) Figure 2. OnRegion Characteristics R DS(on), DRAINTOSOURCE CURRENT ( ).18.16.14.12.1.8.6.4.2 V GS = 1 V T = C T = 25 C T = 55 C 5 15 2 Figure 3. OnResistance versus Drain Current and Temperature R DS(on), DRAINTOSOURCE RESISTANCE ( ).95.9.85.8 T = 25 C V GS = 1 V V GS = 15 V.75 5 15 2 Figure 4. OnResistance versus Drain Current and Gate Voltage R DS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2.5 2. 1.5 1..5 I D = 5 A V GS = 1 V 5 25 25 5 75 125 15 I DSS, LEAKAGE (na) 1 V GS = V T J = 125 C T J = C 1. 2 4 6 8 T J, JUNCTION TEMPERATURE ( C) Figure 5. OnResistance Variation with Temperature V DS, DRAINTOSOURCE VOLTAGE (V) Figure 6. DraintoSource Leakage Current versus Voltage 3
NTYN1 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(AV) ) can be made from a rudimentary analysis of the drive circuit so that t = Q/I G(AV) During the rise and fall time interval when switching a resistive load, V GS remains virtually constant at a level known as the plateau voltage, V SGP. Therefore, rise and fall times may be approximated by the following: t r = Q 2 x R G /(V GG V GSP ) t f = Q 2 x R G /V GSP where V GG = the gate drive voltage, which varies from zero to V GG R G = the gate drive resistance and Q 2 and V GSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: t d(on) = R G C iss In [V GG /(V GG V GSP )] t d(off) = R G C iss In (V GG /V GSP ) The capacitance (C iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 4
NTYN1 2 V DS = V GS = T J = 25 C C, CAPACITANCE (pf) 16 12 8 C iss C rss C iss 4 C oss 1 5 5 1 15 2 25 V gs V ds Figure 7. Capacitance Variation 1 Q T V GS, GATETOSOURCE VOLTAGE (V) 8. 6. 4. V DS Q1 Q2 V GS 2. 2 I DS = A Q3 T J = 25 C 5 15 2 Q g, TOTAL GATE CHARGE (nc) Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge 8 6 4 V DS, DRAINTOSOURCE VOLTAGE (V) t, TIME (nc) 1 V DD = 5 V I D = A V GS = 1 V t f t d(on) t d(off) t r I S, SOURCE CURRENT (A) 8 6 4 2 V GS = V T J = 25 C 1. 1 1 R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation versus Gate Resistance.2.4.6.8 1 V SD, SOURCETODRAIN VOLTAGE (V) Figure 1. Diode Forward Voltage versus Current 5
NTYN1 SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded and the transition time (t r,t f ) do not exceed 1 s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (I D ), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous I D can safely be assumed to equal the values indicated. 1 R DS(on) Limit Package Limit 1 s 1 s 1 s.1 V GS = 2 V 1 ms Single Pulse dc T C = 25 C Thermal Limit.1.1 1 1 V DS, DRAINTOSOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Bias Safe Operating Area E AS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mj) 5 4 3 2 I D = A 25 5 75 125 15 T J, STARTING JUNCTION TEMPERATURE ( C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 6
NTYN1 SAFE OPERATING AREA r (t), EFFECTIVE TRANSIENT THERMAL RESISTANC (NORMALIZED) 1.1 D =.5.2.1.1 SINGLE PULSE.2.5 P (pk).1 1.E5 1.E4 1.E3 1.E2 1.E1 1.E+ 1.E+1 t, TIME (s) t 1 t 2 DUTY CYCLE, D = t 1 /t 2 Figure 13. Thermal Response R JC (t) = r(t) R JC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 T J(pk) T C = P (pk) R JC (t) I S di/ dt t a t rr t b TIME t p.25 I S Figure 14. Diode Reverse Recovery Waveform I S 7
NTYN1 PACKAGE DIMENSIONS TO3BPL (TO264) CASE 34G2 ISSUE J R N F 2 PL Q.25 (.1) M T B M B U A 1 2 3 L P K W G J D 3 PL H.25 (.1) M T B S C T E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 28. 29. 1.12 1.142 B 19.3 2.3.76.8 C 4.7 5.3.185.29 D.93 1.48.37.58 E 1.9 2.1.75.83 F 2.2 2.4.87.12 G 5.45 BSC.215 BSC H 2.6 3..12.118 J.43.78.17.31 K 17.6 18.8.693.74 L 11.2 REF.411 REF N 4.35 REF.172 REF P 2.2 2.6.87.12 Q 3.1 3.5.122.137 R 2.25 REF.89 REF U 6.3 REF.248 REF W 2.8 3.2.11.125 STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85821312 USA Phone: 48829771 or 8344386 Toll Free USA/Canada Fax: 48829779 or 83443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 82829855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 291 Kamimeguro, Meguroku, Tokyo, Japan 15351 Phone: 8135773385 8 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTYN1/D