Class-AB Low-Voltage CMOS Unity-Gain Buffers

Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of magnitude larger than their quiescent current, are good candidates for low-power analog design. This paper presents several new, simple, low-voltage class-ab unity-gain buffers, based on the Flipped Voltage Follower cell and on floating gate transistors. Simulation and experimental results are provided. The proposed circuit has been designed and fabricated in a standard 0.5 μm CMOS technology. Moreover, several improvements to the basic structure are also proposed, analyzed and measured throughout the paper. Index Terms Analog circuits, CMOS analog integrated circuits, low power circuits, low voltage circuits, buffer circuits, floating-gate transistor. M 1 M 2 M 1 M 2 I. INTRODUCTION LASS-AB circuits are good candidates when low C quiescent power consumption is required. They are able to provide currents much larger than the quiescent current, allowing the circuit to drive larger loads at higher frequencies when compared to class-a circuits with the same quiescent current. Therefore, class-ab circuits are a good choice when a low-power design is required. Previously reported CMOS class-ab unity-gain buffers are based on the gate-input buffer of Figure 1a, and on the source-input buffer of Figure 1b [1]. The main drawbacks of these topologies are the reduced linearity and that they require a supply voltage larger than two gate-to-source voltages, which preclude their operation under low voltage conditions. Solutions to these problems have also been proposed in the past, but at the cost of increased circuit complexity, noise and power consumption with a reduction of the bandwidth. In this paper, a new and very simple, low-voltage class- AB buffer based on the flipped voltage follower (FVF) cell is proposed. Although several class-ab analog buffers based on the FVF cell have been reported in the past ([4]-[5]), the main difference between them and the one proposed in this paper is that the analog buffers in [4] and [5] lack of the low-voltage operation capability as they need two stacked transistors turned on in order to operate properly. Manuscript received April 17, 2005. This work was supported in part by the Spanish Ministry of Science and Technology under project TIC2003-07307-C02-01. R.G. Carvajal, Mariano Jiménez and A. Torralba are with the Department of Electronic Engineering, School of Engineering, Universidad de Sevilla, Camino de los Descubrimientos, s/n, Sevilla-41092 (Spain), (phone: +34-95-448 73 63; fax: +34-95-448 73 73; e-mail: {carvajal, mjimenez, torralba}@ gte.esi.us.es). J.Ramírez-Angulo is with the Klipsch School of Electrical Engineering, New Mexico State University (NMSU), Las Cruces, NM 88003-0001. IN M 3 M 4 OUT IN M 3 M 4 a) b) Fig. 1. Classical class-ab unity-gain buffers: a) Gate-input buffer. b) Source-input buffer. OUT II. THE NEW CLASS-AB UNITY GAIN BUFFER. In Fig. 2a the diagram of a conventional voltage follower is presented. This circuit is able to sink a large current when compared to the current that is able to source, which it is only limited by. In Fig. 2b the diagram of the Flipped- Voltage Follower presented in [2] is shown. Opposite to the previous case, the circuit is able to source a large amount of current when compared to the current that is able to sink, which it is also limited by. Both circuits are forced to operate in class-a because must be as large as the maximum required current by the load in order to work properly. In Fig. 2c the proposed buffer is presented. It consists of a combination of the circuits of Figs. 2a and 2b. This circuit is now able to operate in class-ab, sourcing and sinking currents, which can be much larger than the quiescent value. Assuming a capacitive load and quiescent conditions, all transistors are operating in the active region and no current is being delivered to the load. The current through transistor M2 is and, since transistor M1 has the same V SG voltage, the current through M1 will be approximately the same, slightly larger because of the larger V SD. Therefore, the

quiescent current taken from the power supply, under quiescent conditions, can be estimated as 2. There is a DC shift in the output signal (V OUT ) with respect to the input signal (V IN ), expected in this kind of circuits that are operating with a limited headroom in terms of voltage supply. In quiescent conditions V OUT =V IN +V SG M2. Fig. 2. a) Conventional voltage follower. b) Flipped Voltage Follower (FVF). c) Proposed unity-gain buffer. When the input signal V IN increases with respect to the output signal V OUT, transistors M1 and M2 tend to the cutoff region while transistor M3 tends to triode region. This forces a large current through transistor M3 until quiescent conditions are reached again. In this operation regime, the shunt feedback provided by the FVF cell [2] leads to a very low output resistance given by 1/(gm 2 gm 3 ro 2 ), where, as usual, gm i and ro i are the transconductance and output resistance of transistor Mi, respectively. In the opposite case, with the input signal V IN decreasing with respect to the output signal V OUT, transistor M2, tends to triode region causing the voltage V SG of transistor M3 to decrease thus, driving transistor M3 to the cutoff region. Transistor M1 remains in saturation and since it is not limited by, is able to sink a large current until again, quiescent conditions are reached. In this operation regime, the output resistance is approximately given by 1/gm 1. This circuit requires a minimum supply voltage given by V DD MIN =max{v SG M2 +V SD M3 +V S, V SG M3 +V DS Mb +V S }, where Mb is the n-mos transistor which implements the current source Ib. V S is the desired signal swing which can be as high as (V SG M 3-V EFF M3 -V EFF M2 ). V DD MIN can be as low as 1.2V+V S for a 0.5 µm standard CMOS technology with a pmos threshold voltage of -0.9V approximately. A. Design Considerations. The proposed buffer has different resistance paths for charging and discharging the load capacitor, which limits the circuit operation to the speed of the slowest path (the discharging path in this case). Transistors M1 and M2 can be designed larger than M3 to reduce the difference between the rise and fall times but it is not possible to equalize the times with appropriate V DS values for all transistors. Several solutions to this fact will be explored within this paper. The proposed buffer features a gain that is slightly lower than unity. This is due to the finite impedance of transistor M2. The transistor sizes (W/L in µm) for the designed buffer are 45/0.6, for all PMOS transistors and 15/0.6 for all NMOS transistors. B. Stability of the buffer. Assuming a capacitive load and an ideal input voltage source, the stability of the proposed buffer is determined by the stability of the FVF section. If the current source is implemented by a simple current mirror, the stability condition for the FVF section leads to CX/CY<gm2/(4gm3), where CX and CY are the equivalent capacitances at nodes X and Y, respectively, including the load capacitor. For small capacitive loads this condition is easily achieved by proper sizing of transistors M2 and M3. Otherwise, a compensating capacitor C C would be required between the gate and the drain of transistor M3 to increase the equivalent capacitance at node Y. C. Mismatch effects on the circuit performance. The proposed circuit is naturally robust to mismatch, mainly because it has no differential input stage and no need to match any pair of transistors. The voltage at the output node depends mainly on transistor M2, and with a little influence on transistor M1. Variations of around ten percent in the three transistors were simulated which caused variations of a few milivolts in the DC shift level, almost no variation in the output signal swing, and negligible variations in the circuit speed. In conclusion, this circuit is very robust against mismatch. In order to improve the THD performance of the circuit (degraded by the different resistance paths for charging an discharging the load), this buffer can be used with a differential signal by simply using two buffers. Special care must be taken to match both buffers or at least place them as close as possible, because mismatch will lead to distortion problems. However, the buffer has a much better distortion performance using a differential signal in spite of any mismatch issue. This is because the THD performance of the proposed buffer is mainly dominated by the second harmonic, as it will be shown next. D. Noise Behavior. The simplicity of the circuit also helps for the noise performance. From simulations, a voltage noise density of around 10nV/ Hz was estimated for the designed buffer. E. Simulation and measurement results. The circuit was designed using a standard 0.5µm CMOS technology. It was simulated and tested using a 1.5V supply. The selected bias current it is of 20µA. The circuit was simulated and measured with an output capacitance of 18pF including pad and probes. In fig. 3 the simulated output for a 1.56 Mhz, 200mV square input signal is presented. The represented currents are the one going through M3, which is also the current drained from the power supply (continuous line) and the current through the load capacitor (dotted line). It can be observed how, during the rise time, most of the current is used to charge the load capacitor and, the rest of the time, only the bias current is drained from the power source. From these simulations, we can estimate a quiescent power consumption of 60 µw and a total power consumption of 75 µw. This confirms the class AB operation of the circuit.

a) Fig 3. Simulated output current for a 1.56 MHz, 200 mv square input signal. Fig. 4 shows the measured response for a 1.56 Mhz, 200mV square input signal, input and output signals are presented, the predicted slower fall signal it is observed at the output. Fig 5 shows the buffer response for a 2 Mhz sinusoidal input signal, input and output signals are overlapped in the figure. In fig. 6a the signal harmonics are shown and, since the circuit is single ended configuration, the second harmonic is the dominant one. A differential version will reduce the second harmonic and improve buffer performance as can be observed in figure 6b. The chip microphotograph is shown in fig. 7. b) Fig.6. Measured THD of the proposed analog buffer: a) single ended configuration, b) differential configuration. Fig 4. Measured transient response of the buffer in g fig. 2c, using a 1.56 MHz, 200 mv square input signal. Fig 7. Microphotograph of the buffer in figure 2c. In the next sections, we are going to present several solutions for the improvement of the rise and fall times as well as the linearity and the DC level shift of the proposed buffer. Fig 5. Measured transient response of the buffer in g fig. 2c, using a 5 MHz, 200 mv peak-to-peak sinusoidal input signal. III. BUFFER WITH NO DC LEVEL SHIFT AND IMPROVED LINEARITY The linearity of the presented buffer can be improved if we use an Op-Amp in negative feedback loop as it is shown in Fig. 8. The main advantages of this modification are: a) Same DC level in the input and output signal, b) better distortion performance, c) buffer gain closer to the unity than in the previous case and d) the input capacitance can be

scaled down if we use minimum transistor sizes for the Op- Amp. However, the Op-Amp introduces a feedback between the output and input nodes, which can cause stability problems if the Op-Amp GBW is not selected properly. Moreover, the power consumption and the noise also increase because of the Op-Amp. A. Measurement results. The circuit was tested at a low frequency to observe improvements compared to the previous buffer. Fig 9 shows the buffer response for a 10Khz input signal (Input and output signals are overlapped). Since this circuit has the same DC level for the input and output, both signals shown in the figure have a DC level of 200mV and a 360mV peak to peak voltage. Harmonics are show in fig. 10, and the highest is about 65 db below the signal, which is a much better result than the previous buffer, which measured about 57 db at the same frequency. Fig 8. Proposed buffer with no DC level shift and improved linearity. For this particular case, the buffer has been designed using NMOS transistors instead of the PMOS used in the previous buffer. With NMOS transistors in the buffer, the Op-Amp must have a PMOS differential pair input when operated in a low-voltage environment. The body effect can be easily eliminated in our technology for the PMOS input pair of the Op-Amp as we are using an N-well CMOS technology. Since the charging and discharging paths of the load capacitor are the same than in the previous case, the same problem of one path significantly slower than the other remains. Fig 10. Measured THD of the analog buffer in figure 8. IV. THE FLOATING GATE TRANSISTOR BUFFER In the originally proposed buffer of section II the transistor charging the load is controlled by a different node than the one discharging it. This is the main reason we have different resistance paths. The buffer shown in fig. 11 has been devised using floating gate (FG) transistors [6] and overcomes this problem as the drain of M2 has control over the charging and discharging transistors (M3 and M1, respectively). This new design has now a greater control over the fall time and it is possible to equalize it with the rise time. Fig. 11. Proposed buffer using Floating-Gate transistors Fig 9. Measured transient response of the buffer in g fig. 8, using a 10 khz, 360 mv peak-to-peak sinusoidal input signal. The circuit works in a similar way than the one proposed in section II. The main differences are: a) the need of a replica bias circuit (M b1, M b3 ) to properly set the quiescent current through M1 to (i.e. to set the quiescent voltage at

node Y), b) Node Y controls now transistors M3 and M1 that charge or discharge the load capacitance what makes similar the rising and falling times of the output voltage. The two main disadvantages of the FG buffer are the increased complexity, and the increased power consumption, which is four times higher than in the buffer of section II. Also FG transistors use more area in an integrated circuit. Stability issues require special care for this buffer. A compensating capacitance was required between the output node and the control node Y in order to make node Y the dominant pole. A. Measurement results. The FG buffer features an improved rise and fall time equalization as expected, and this fact is shown in the fig. 12. The harmonics for a 10khz sinusoidal input signal are shown in fig. 13 and, it can be observed how the linearity of this buffer is also high with a second harmonic 59.7dB below the signal. source connected to the lowest voltage. The circuit must be designed in order keep the voltage V GS M4, always below the transistor threshold voltage when the circuit is in quiescent conditions in the entire output range. Therefore, transistor M4 will be in the cutoff region under quiescent conditions, and since the voltage at the drain of M2 is even lower when charging the output capacitor, it will be also in the cutoff region during the rise time of the input signal. Transistor M4 will be turned on only during the fall time of a signal that requires more than 2 to discharge the output capacitor. During the fall time, the voltage at the gate of M4 tends to increase, and if the signal is fast enough it will increase beyond the NMOS threshold voltage, turning on transistor M4, which helps to discharge the output capacitor. The transistor stays on until its gate voltage is again below the threshold, and the operation of the buffer continues like in the original buffer of the section II, till quiescent conditions are reached again. M 3 OUT IN M 2 M 1 M 4 Fig. 12.Measured transient response of the buffer in g fig 11, using a 200 khz, 200 mv square input signal. Fig. 14. Proposed buffer with improved fall time. This very simple modification helps to reduce the differences between the rise and fall times with no extra power consumption. However, the charging and discharging paths of the output capacitor are still different, and distortion is still expected, but the improvement with respect to the buffer of section II is substantial. The proposed modification restricts the operation of this buffers to V DD values that satisfy V DD <V TP +V TN, to prevent transistor M$ to be turned on under quiescent conditions. This is easy to satisfy as the family of buffers proposed in this paper are intended for low voltage operation. Fig. 13. Measured THD of the analog buffer in figure 11. V. THE BUFFER WITH IMPROVED FALL TIME The buffer shown in Fig 14, is a very simple modification for the buffer proposed in section II. An NMOS transistor M4, has been added with the gate connected to the drain of M2, the drain connected with the output node, and the A. Measurement results. The expected fall time improvement can be observed in fig. 15 (for this buffer the NMOS transistor was not calculated accurately, and the discharging path has now a lower resistance than the charging one). However, from simulations was determined that the path resistances can be designed to be almost identical. The circuit harmonics was also tested and as expected, no significant differences were observed with respect to the

original buffer presented in section II. The harmonics measurement is presented in fig 16, with a third dominant harmonic 59.7 db s below the input signal. VI. CONCLUSION A new class-ab unity-gain buffer based on the Flipped Voltage Follower (FVF) has been proposed. This circuit can be operated at a low supply voltage with high linearity. Experimental results have been provided that show the class- AB functionality of the proposed circuit with a low supply voltage (1.5 V) using a 0.5 µm CMOS standard technology. Several improvements to the basic topology have been also proposed and experimentally verified. TABLE I shows a comparison of the main performance parameters of the proposed buffers. Fig 15. Measured transient response of the buffer in g fig 14, using a 200 khz, 200 mv square input signal. REFERENCES [1] D.M. Monticelli, A quad CMOS single-supply opamp with rail-torail output stage, IEEE J. Solid-State Circuits, vol. SC-21, pp. 1026-1034, Dec. 1986. [2] J. Ramírez-Angulo, R.G.Carvajal, A.Torralba, J.Galán, A.P. Vega- Leal, J.Tombs, The Flipped Voltage Follower: a useful cell for lowvoltage low-power circuit design, in Proc. of the IEEE Int. Symp. on Circuits and Systems, vol. 3, pp. 615-618, May 2002. [3] H.Elwan, M.Ismail, CMOS low noise class AB buffer, Electronics Letters, vol. 35, 21, pp. 1834-1835, October 1999. [4] A.Torralba, R.G.Carvajal, J.A.Galán, J.Ramírez-Angulo. Compact low-power, high slew-rate CMOS buffer for large capacitive loads IEE Electronics Letters, vol. 38, no. 22, pp. 1348-1349, 24th Oct. 2002. [5] J.M. Carrillo. R.G. Carvajal, A. Torralba and F. Duque-Carrillo. Rail-to-rail low-power high-slew-rate CMOS analog buffer IEE Electronics Letters, Volume: 40, Issue: 14, pp. 843-844, 8 July 2004. [6] E. Rodriguez-Villegas and H. Barnes, Solution to trapped charge in FGMOS transistors, Electronics Letters, vol. 39, no. 19, 18 Sept. 2003, pp. 1416-1417 Fig 17. Measured THD of the analog buffer in figure 14 Original Buffer Op-Amp Feedback Floating Gate Buffer N driver Buffer Maximum Frequency Static Power THD @ 10Khz Buffer Area (µm 2 ) 5 Mhz 0.8Mhz 2.5Mhz 5 Mhz 60µW 120µW 120µW 60µW -52dB -59dB -54dB -52dB 50 x 100 280 x 100 210 x 140 60 x 100 Main advantage Simplicity in design Very high linearity Improved linearity at high freq. Improved linearity at high freq. Main drawback Poor control of pulse fall time High static power, Stability High static power Only suited for low voltage TABLE I: Comparison of the proposed analog buffers