CA Data Sheet November 999 File Number 6.6 Dual High Frequency Differential Amplifier For Low Power Applications Up to MHz The CA consists of two independent differential amplifiers with associated constant current transistors on a common monolithic substrate. The six transistors which comprise the amplifiers are general purpose devices which exhibit low /f noise and a value of f T in excess of GHz. These features make the CA useful from DC to MHz. Bias and load resistors have been omitted to provide maximum application flexibility. The monolithic construction of the CA provides close electrical and thermal matching of the amplifiers. This feature makes this device particularly useful in dual channel applications where matched performance of the two channels is required. The CA has a separate substrate connection for greater design flexibility. Ordering Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. NO. CAE - to 4 Ld PDIP E4. CAM () - to 4 Ld SOIC M4. Features Power Gain db (Typ)..................... MHz Noise Figure 4.6dB (Typ)................... MHz Two Differential Amplifiers on a Common Substrate Independently Accessible Inputs and Outputs Full Military Temperature Range....... - o C to o C Applications VHF Amplifiers VHF Mixers Multifunction Combinations - RF/Mixer/Oscillator; Converter/IF IF Amplifiers (Differential and/or Cascode) Product Detectors Doubly Balanced Modulators and Demodulators Balanced Quadrature Detectors Cascade Limiters Synchronous Detectors Balanced Mixers Synthesizers Balanced (Push-Pull) Cascode Amplifiers Sense Amplifiers Pinout CA (PDIP, SOIC) TOP VIEW 4 4 SUBSTRATE SUBSTRATE 6 7 9 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or 47-77-97 Copyright Intersil Corporation 999
CA Absolute Maximum Ratings Collector-to-Emitter Voltage, V CEO...................... V Collector-to-Base Voltage, V CBO........................ V Collector-to-Substrate Voltage, V CIO (Note ).............. V Emitter-to-Base Voltage, V EBO.......................... V Collector Current, I C................................ ma Operating Conditions Temperature Range......................... - o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package............................. SOIC Package............................. Maximum Power Dissipation (Any One Transistor)....... mw Maximum Junction Temperature (Plastic Package)....... o C Maximum Storage Temperature Range.......... -6 o C to o C Maximum Lead Temperature (Soldering s)............ o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. The collector of each transistor of the CA is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH Input Offset Voltage (Figures, 4) V IO -.. mv Input Offset Current (Figure ) I IO I = I 9 = ma -.. µa Input Bias Current (Figures, ) I B -. µa Temperature Coefficient Magnitude of Input Offset Voltage V IO ---------------- T DC CHARACTERISTICS FOR EACH TRANSISTOR -. - µv/ o C DC Forward Base-to-Emitter Voltage (Figure 6) VBE V CE = 6V, I C = ma 674 774 874 mv Temperature Coefficient of Base-to-Emitter Voltage (Figure 6) V BE -------------- T V CE = 6V, I C = ma - -.9 - mv/ o C Collector Cutoff Current (Figure 7) I CBO V CB = V, I E = -. na Collector-to-Emitter Breakdown Voltage V (BR)CEO I C = ma, I B = 4 - V Collector-to-Base Breakdown Voltage V (BR)CBO I C = µa, I E = 6 - V Collector-to-Substrate Breakdown Voltage V (BR)CIO I C = µa, I B = I E = 6 - V Emitter-to-Base Breakdown Voltage V (BR)EBO I E = µa, I C = 7 - V DYNAMIC CHARACTERISTICS FOR EACH /f Noise Figure (For Single Transistor) (Figure ) NF f = khz, R S = Ω, I C = ma -. - db Gain Bandwidth Product (For Single Transistor) (Figure ) f T V CE = 6V, I C = ma -. - GHz Collector-Base Capacitance (Figure 8) C CB I C =, V CB = V Note -.8 - pf Note 4 -. - pf Collector-Substrate Capacitance (Figure 8) C CI I C =, V CI = V -.6 - pf Common Mode Rejection Ratio CMRR I = I 9 = ma - - db AGC Range, One Stage (Figure ) AGC Bias Voltage = -6V - 7 - db Voltage Gain, Single-Ended Output (Figures, 9, ) A Bias Voltage = -4.V, f = MHz 8 - db
CA Electrical Specifications (Continued) Insertion Power Gain (Figure ) G P V CC = V, for Cascode - - db Noise Figure (Figure ) NF Cascode Configuration Cascode - 4.6 - db Input Admittance Y I =I 9 = ma. For Diff. Amp. Cascode (Figures 4, 6, 8) -. + j.4 - ms Configuration Diff. Amp. (Figures -.878 + j. - ms I =I 9 = 4mA (Each, 7, 9) Collector I C ma) Reverse Transfer Admittance Y f = MHz Cascode -. - j.8 - ms Diff. Amp. -. - j. - ms Forward Transfer Admittance PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Y Cascode (Figures 6, 8, ) Diff. Amp. (Figures 7, 9, ) Output Admittance Y Cascode (Figures,, 4) NOTES:. Terminals and 4 or 7 and 8. 4. Terminals and 4 or 6 and. Diff. Amp. (Figures,, ) - 7.9 - j.7 - ms - -. + j - ms - -. - j - ms -.7 + j.6 - ms Schematic Diagram CAE, CAM 4 4 8 7 6 Q Q Q 6 Q Q Q 4 SUBSTRATE 9
CA Test Circuits +6V V+ (+6V) kω V OUT +V (7) 4 (6) kω M S kω kω µf (8) Q S Q V 4 V IN O M (Q 6 ) (Q ) () -V S S Ω BIAS VOLTAGE () Q (Q 4 ) Ω (9) V X M I or I 9 Ω V- (-6V) FIGURE. DC CHARACTERISTICS TEST CIRCUIT FOR CA FIGURE. AGC RANGE AND VOLTAGE GAIN TEST CIRCUIT FOR CA -6V / CA 4(7).µF (8) Q (Q 6 ) Q (Q ) () SUBSTRATE Q (Q 4 ) () (9) 4 () (6) INPUT R G = Ω.6pF µf C L Ω 6V +. µf pf C.µF.7pF L OUTPUT R L = Ω.µF kω pf.µf kω pf MA kω FERRITE BEADS 47pF kω kω.µf pf NOTES:. Numbers in parentheses refer to the other half of the CA. 6. L,L - Approximately / Turn #8 Tinned Copper Wire, /8 Diameter. 7. C,C - pf Variable Capacitors (Hammarlund, MAC-; or Equivalent). +V.µF FIGURE. MHz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT 4
CA Typical Performance Curves. INPUT OFFSET VOLTAGE (mv).4. INPUT BIAS CURRENT (µa). T A = -4 o C T A = 8 o C.. EMITTER CURRENT (ma) FIGURE 4. INPUT OFFSET VOLTAGE vs EMITTER CURRENT... EMITTER CURRENT (ma) FIGURE. INPUT BIAS CURRENT vs EMITTER CURRENT BASE-TO-EMITTER VOLTAGE (V)..9.8.7.6 T A = 8 o C T A = -4 o C... COLLECTOR CURRENT (ma) FIGURE 6. BASE-TO-EMITTER VOLTAGE vs COLLECTOR CURRENT COLLECTOR CUTOFF CURRENT (pa).. V CB = V V CB = V V CB = V. - -7 - - 7 TEMPERATURE ( ο C) FIGURE 7. COLLECTOR CUTOFF CURRENT vs TEMPERATURE 7 6 4 V+ = 6V, V- = -6V f = khz CAPACITANCE (pf) C CI TERMINALS 4 AND ; 7 AND 8 TERMINALS AND 4; 6 AND VOLTAGE GAIN (db) - - - C CB 4 6 7 8 9 4 BIAS VOLTAGE (V) -4 - - - - -4 - -6-7 BIAS VOLTAGE ON TERMINALS AND (V) FIGURE 8. CAPACITANCE vs DC BIAS VOLTAGE FIGURE 9. VOLTAGE GAIN vs DC BIAS VOLTAGE
CA Typical Performance Curves (Continued) 4. VOLTAGE GAIN (db)... GAIN BANDWIDTH PRODUCT (GHz).9.8.7.6..4.....9.8 4 6 7 8 9 4 COLLECTOR CURRENT (ma) FIGURE. VOLTAGE GAIN vs FREQUENCY FIGURE. GAIN BANDWIDTH PRODUCT vs COLLECTOR CURRENT R SOURCE = Ω f = Hz R SOURCE = kω f = Hz f = Hz NOISE FIGURE (db) f = khz f = khz f = Hz f = khz NOISE FIGURE (db) f = khz f = khz... COLLECTOR CURRENT (ma) FIGURE. /f NOISE FIGURE vs COLLECTOR CURRENT f = khz... COLLECTOR CURRENT (ma) FIGURE. /f NOISE FIGURE vs COLLECTOR CURRENT INPUT CONDUCTANCE (g ) (ms)..... V CC = V I = I 9 = ma g INPUT SUSCEPTANCE (b ) (ms) INPUT CONDUCTANCE (g ) OR SUSCEPTANCE (b ) (ms) 6 4 V CC = V I = I 9 = 4mA b g b FIGURE 4. INPUT ADMITTANCE (Y ) vs FREQUENCY FIGURE. INPUT ADMITTANCE (Y ) vs FREQUENCY 6
CA Typical Performance Curves (Continued) INPUT CONDUCTANCE OR b g I = I 9 = ma f = MHz INPUT CONDUCTANCE OR I = I 9 = 4mA f = MHz b g 4 4 FIGURE 6. INPUT ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE FIGURE 7. INPUT ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE INPUT CONDUCTANCE OR 7 6 4 V CC = V f = MHz b g INPUT CONDUCTANCE OR V CC = V f = MHz g b 4 6 8 EMITTER CURRENT (I OR I 9 ) (ma) EMITTER CURRENT (I OR I 9 ) (ma) FIGURE 8. INPUT ADMITTANCE (Y ) vs EMITTER CURRENT FIGURE 9. INPUT ADMITTANCE (Y ) vs EMITTER CURRENT - - - -4 - V CC = V I = I 9 = ma b g 4 - V CC = V I = I 9 = 4mA b g -6 FIGURE. OUTPUT ADMITTANCE (Y ) vs FREQUENCY - FIGURE. OUTPUT ADMITTANCE (Y ) vs FREQUENCY 7
CA Typical Performance Curves (Continued) - - g b I = I 9 = ma f = MHz.6.4. b g I = I 9 = 4mA f = MHz - 4 FIGURE. OUTPUT ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE 4 FIGURE. OUTPUT ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE - - - V CC = V f = MHz 4 6 8 EMITTER CURRENT (I OR I 9 ) (ma) FIGURE 4. OUTPUT ADMITTANCE (Y ) vs EMITTER CURRENT g b V CC = V f = MHz - EMITTER CURRENT (I OR I 9 ) (ma) FIGURE. OUTPUT ADMITTANCE (Y ) vs EMITTER CURRENT b g FORWARD TRANSFER CONDUCTANCE (ms) 7 6 V CC = V I = I 9 = ma g T A = o C 4 - - b - -4 FORWARD TRANSFER FORWARD TRANSFER CONDUCTANCE OR 4 V CC = V I = I 9 = 4mA b g - - - -4 FIGURE 6. FORWARD TRANSFER ADMITTANCE (Y ) vs FREQUENCY FIGURE 7. FORWARD TRANSFER ADMITTANCE (Y ) vs FREQUENCY 8
CA Typical Performance Curves (Continued) FORWARD TRANSFER CONDUCTANCE OR - - - g I = I 9 = ma f = MHz b FORWARD TRANSFER CONDUCTANCE OR - - b g I = I 9 = 4mA f = MHz - 4 FIGURE 8. FORWARD TRANSFER ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE FIGURE 9. FORWARD TRANSFER ADMITTANCE (Y ) vs COLLECTOR SUPPLY VOLTAGE FORWARD TRANSFER CONDUCTANCE OR 4 g - - - V CC = V f = MHz -4 - -6 b -7-8 4 6 8 4 EMITTER CURRENT (I OR I 9 ) (ma) FORWARD TRANSFER CONDUCTANCE OR 4 - V CC = V f = MHz - 4 8 6 EMITTER CURRENT (I OR I 9 ) (ma) b g FIGURE. FORWARD TRANSFER ADMITTANCE (Y )vs EMITTER CURRENT FIGURE. FORWARD TRANSFER ADMITTANCE (Y )vs EMITTER CURRENT 9
CA Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9. 4. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8., E6., E8., E8., E4.6 will have a B dimension of. -.4 inch (.76 -.4mm). -B- A. (.) M C A A L BS A e C E C L e A C e B E4. (JEDEC MS--AA ISSUE D) 4 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -. -. 4 A. -.9-4 A..9.9 4.9 - B.4..6.8 - B.4.7..77 8 C.8.4.4. - D.7.77 8.66 9.68 D. -. - E.. 7.6 8. 6 E.4.8 6. 7. e. BSC.4 BSC - e A. BSC 7.6 BSC 6 e B -.4 -.9 7 L...9.8 4 N 4 4 9 Rev. /9
CA Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.(.) M B A.(.4) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.6mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.4 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α L M h x 4 o C M4. (JEDEC MS--AB ISSUE C) 4 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A..688..7 - A.4.98.. - B.... 9 C.7.98.9. - D.67.444 8. 8.7 E.497.74.8 4. 4 e. BSC.7 BSC - H.84.44.8 6. - h.99.96.. L.6..4.7 6 N 4 4 7 α o 8 o o 8 o - Rev. /9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 88, Mail Stop -4 Melbourne, FL 9 TEL: (47) 74-7 FAX: (47) 74-74 EUROPE Intersil SA Mercure Center, Rue de la Fusee Brussels, Belgium TEL: ().74. FAX: ().74.. ASIA Intersil (Taiwan) Ltd. 7F-6, No. Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 76 9 FAX: (886) 7 9