Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Lecture 9 MOS Logic and Gate Circuits B B Y Wired OR dib brishamifar EE Department IUST

Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear Enhancement Load Depletion Load Some Gates Transient in NMOS Circuit Pseudo-NMOS CMOS Logic Static CMOS Logic Gates NOT NND NOR Realization of More Complicated Gate Circuits Transmission Gates Family NMOS Only Switch CMOS Differential Cascode Voltage Switch Logic Rules of Thumb Summary 2/126

Introduction The MOS inverter is the basic circuit exhibits all of the essential features of MOS Logic. Extension of MOS inverter concepts to NOR and NND Gate is very simple. In this lecture we will analysis for VTC, NM, PD,. Both NMOS and CMOS circuits are considered. Digital MOS circuits can be classified into two categories: Static Circuits: require no clock or other periodic signal for operation. Clocks are required for static circuit in sequential logic Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic 3/126

NMOS Logic Resistive Load W VoL C Speed L P RL rea Vo Vdd Vi +Vdd RL Vo V OL o Vi 5/126

NMOS Logic Resistive Load Properties N transistors + Load V OH = Vdd V OL = Vdd ( rn/(rn + RL)) ssymetrical response Static power consumption t PL = 0.69RLCL 6/126

NMOS Logic Saturated Enhancement Load Vds2= Vgs2 + Vdd + Vdd Vds2> Vgs2 V Vo V OH δvo δvi = 1 T2 M2 is in saturation Vi M2 M1 Vo β R V OL o V IL Vi V IH 8/126

NMOS Logic Saturated Enhancement Load V IL V V M1, M2 are in saturation IL T1 K(Vgs1 V ) = K(Vgs2 V ),V Cte 2 2 1 T1 2 T2 δvo Vgs1= Vi, Vgs2= Vdd Vo = βr, β R > 1 δvi δvo 1 VI L VT 1 δvi T2 Vo V OH V OL o δvo δvi V IL V IH = 1 β R Vi 9/126

NMOS Logic Saturated Enhancement Load V OL V OL is difficult to obtain because it is the output voltage when input equal to V OH, the resulting expression is a fourth order polynomial! Vo V OH δvo δvi = 1 β R V OL o V IL Vi V IH 10/126

NMOS Logic Saturated Enhancement Load V IH M1 is in triode and M2 in saturation δvo δi1 = δvi δvi δvo rds1rds2 rds1 = δ i ( rds1rds2) ( ) 1 i2 = K(Vgs2 2 V T2) 2 δi1 = KVo 1 δvi 2 i1 = K1 Vgs1 VT1 Vo Vo 2 1 2 δi δvo K ( Vgs1 V Vo) δvo KVo δvi K(Vgs1 V Vo) 1 = 1 T1 1 = = Vo = Vi V 2 V 1 T1 T1 V IH T1 Vi = VIH = Vo 2 1 11/126

NMOS Logic Saturated Enhancement Load V IH M1 is in triode and M2 in saturation i = i 1 2 1 K ( V V ) Vo Vo 2 = K(Vdd Vo V ) 2 2(Vdd V ) VT1 3β + 1 2 2 1 IH T1 2 T2 T2 VIH = + R 12/126

NMOS Logic Saturated Enhancement Load NM NML = V V Some tenth of volt IL OL NMH = V V = Vdd V V OH IH T2 IH Power P 0, P = IVdd dish disl d P = 12IVdd dis d 13/126

NMOS Logic Linear Enhancement Load VGG Vdd+ V T2 M2 is in triode Linear Enhancement Load VGG Vi +Vdd M2 Vo M1 15/126

NMOS Logic Linear Enhancement Load VTC By this circuit the V OH can be increased (or Vdd can be decreased because Vo max = Vdd ) Vo Vdd V OL o V IL Vdd Vi V T V IH 16/126

NMOS Logic Linear Enhancement Load V IL M1 is in saturation and M2 in triode δvo δi1 δi1 δvds2 = rds2 = δvi δvi δvi δi ( ) δi2 = K2( VGG Vo VT2 δvds2 Vds2) 2 i2 = K2 Vgs2 VT2 Vds2 Vds2 2 1 1 2 i1 = K(Vi 1 V T1) 2 δi1 = K1( Vi VT1 ) δvi δvo K(Vi 1 V T1) = 1 = δvi K(VGG Vo V Vds2) V = f(vo) IL 2 T2 V IH M1 and M2 are in triode rds2 rds1rds2 17/126

NMOS Logic Linear Enhancement Load Disadvantages: More chip area is required (since an extra voltage source VGG) dditional interconnection on the chip is needed β R The required value of is even larger than a saturated load VGG Vi +Vdd M2 Vo M1 18/126

NMOS Logic Depletion Load Ion implantation processing step is needed to create depletion device, but overcome the disadvantages of the previous circuit +Vdd M2 Vo Vi M1 20/126

NMOS Logic Depletion Load VTC Vi = Low i = 0, M1 in cutoff i = i = 0 1 1 2 K2 2 if M2 is in saturation then i 2 = (Vgs2 V T2),Vgs2= 0 i2 > 0 2 Therefore M2 is in triode Vo Vdd V OL o V IL V T V IH Vdd Vi 21/126

NMOS Logic Depletion Load V OL, V IL, V IH 2 K 2 2 K 1( VOH VT1) VOL VOL 2 = (0 V T2) V OL =? 2 δvo K(Vgs1 V ) = = = = δvi K(Vgs2 V Vds2) 1 T1 1 1, i1 i2 V IL? 2 T2 2 K 2 2 δvo i1 = K 1( VIH VT1) Vds1 Vds1 2 = i 2 = (0 V T2), = 1 V IH =? 2 δvi 22/126

NMOS Logic Some Gates In all previous structures which different only in load, the following Gates can be implemented. Note that the NMOS Gates are not available as separately packaged individual circuits, but they are used extensively in LSI systems NOR Gates NND Gates 24/126

NMOS Logic Some Gates NOR Gate +Vdd M1 B RL M2 Y B Y 25/126

NMOS Logic Some Gates NND Gate +Vdd RL M2 Y B Y B M1 26/126

NMOS Logic Some Gates In NOR Gate two transistors are paralleled but in NND Gate two transistors are in series. Because of the need for increased area when adding NND inputs, NND logic with more than 2 inputs is not economically be attractive in NMOS. NOR logic is preferable In NND the M2 has body effect In NOR we need the less interconnection (this can be shown from layout) 27/126

NMOS Logic Transient in NMOS Circuits Saturated Enhancement Load For transient calculation we need the total capacitance in output. Some of these are voltage dependent. For all of these: 1 2 1 1 Q Q(V2) Q(V1) 2ΦoCjo ( ) 2 ( ) 2 eq = = = Φo Φo C V2 V1 V V2 V1 V2 V1 29/126

NMOS Logic Transient in NMOS Circuits Saturated Enhancement Load +Vdd M2 Cgs2 Cgd1 +Vdd Cs sub2 CL Vo Vi M1 Cd sub1 C = C + Ceq + Ceq + Cgs2+ 2 Cgd1 tot L d sub1 s sub2 30/126

NMOS Logic Transient in NMOS Circuits fter calculation of total capacitance, we need know the average current which this cap. discharge by it I c V 1 = i(v)dv c V o Vi: High to Low or Vo: V OL to V OH V OH 1 1 I = i(vo)dvo,v 0 I i(vo)dvo c 2 OL c 2 VOH VOL V VOH OL VOH K2 2 K2 2 K2 2 2 = T2 c T2 OH 2 2V = OH 6 i (Vdd Vo V ) I (Vdd Vo V )dvo V V = Vdd V OH T2 C It = C V t = V = 6C tot tot c off tot OH off OH Ic KV 2 OH O V OH O 31/126

NMOS Logic Transient in NMOS Circuits Vi: Low to High then M2 is in saturation, but M1 is in triode at first and then in saturation VOH VT2 o 1 K 1 2 2 I = (Vgs1 V T1)dVo K1 ( Vgs1 VT1 ) Vo Vo 2 dvo V + OH V 2 OH VOH VT2 K K I = ( V V ) V + 23V ( V ) (V V ) 2V 3 1 2 1 2 OH T1 T1 OH T1 OH T1 OH This current do not discharge output capacitor, some of current is drawn of M2. Then: K1 2 K2 2 Ic = I I 2 = (VOH V T1) VOH 3 6 C It = C V t = V = 6C V tot tot OH c on tot OH on OH 2 I c 2 VOH K12( VOH VT1 ) βr 1 1 t = t, t = t 2 2 1 t Pd = (tphl + t PLH ) 2 PHL on PLH off 32/126

NMOS Logic Super Buffer (1) If Fan-out is very large then C tot will be large. For reduction it and decrease the switching time the Super Buffer circuit is used In this circuit if Vi is Low state then V1 will be high very more rapid than Vo. Thus the Gate of M2 is in high state very rapidly. Therefore M2 will be in saturation which result the reduction of switching time (t on ) +Vdd +Vdd M4 M2 V1 Vo M1 M3 Vi Super Buffer (1) Circuit 33/126

NMOS Logic Super Buffer (2) It is non-inverting Describe the operation of this circuit! M4 +Vdd +Vdd M2 Vi V1 M1 M3 Vo Super Buffer (2) Circuit 34/126

NMOS Logic Pseudo-NMOS What makes a circuit fast? I = C dv/dt -> tpd (C/I) DV low capacitance high current small swing Logical effort is proportional to C/I PMOS are the enemy! High capacitance for a given current Can we take the PMOS capacitance off the input? Various circuit families try to do this 36/126

NMOS Logic Pseudo-NMOS In the old days, NMOS processes had no PMOS Instead, use pull-up transistor that is always ON In CMOS, use a PMOS that is always ON Make PMOS about ¼ effective strength of pulldown network 37/126

NMOS Logic Pseudo-NMOS Uses a p-type as a resistive pullup, n-type network for pulldowns +Vdd M2 Vo Vi M1 38/126

NMOS Logic Pseudo-NMOS Characteristics Compared to CMOS, this family has higher packing density, since for n inputs only n+1 transistors are required The main disadvantages with Pseudo-NMOS Gates is the large static power dissipation that occurs whenever a pulldown path is activated Has much smaller pullup network than static gate Pulldown time is longer because pullup is fighting Vi +Vdd M2 Vo M1 39/126

NMOS Logic Pseudo-NMOS Output Voltages Logic 1 output is always at Vdd Logic 0 output is above Vss V OL = 0.25 (Vdd -Vss) is one plausible choice +Vdd M2 Vo Vi M1 40/126

NMOS Logic Pseudo-NMOS Design Topics For logic 0 output, pullup and pulldown form a voltage divider Must choose n, p transistor sizes to create effective resistances of the required ratio Effective resistance of pulldown network must be computed in worst case series n-types means larger transistors Vi +Vdd M2 Vo M1 41/126

NMOS Logic Pseudo-NMOS Transistor Ratio Calculation In steady state logic 0 output ( for dual supply) pullup is in linear region V ds = V out -(Vdd or Vss) pulldown is in saturation Pullup and pulldown have same current flowing through them Equate two currents +Vdd I dp = I dd Using 0.5 um parameters, 3.3V power supply W p /L p / W n /L n = 3.9 This is not suitable when use single supply! Vi M2 M1 Vo Vss 42/126

NMOS Logic Pseudo-NMOS Transistor Ratio Calculation MOSFET sizing is important Need to have reasonable W/L ratios for circuit to work correctly V OL >VSS but must be low enough to turn off/on next MOSFET in the chain Static current drain when on Vout is a function of the number of parallel and series N channels in the pull down network 43/126

NMOS Logic Pseudo-NMOS Transistor Ratio Calculation For single supply V OH = Vdd, For the worst case one NMOS to be on 2 V K K Vdd V V Vdd V 2 2 OL P ( ) = ( ) n Tn OL TP K V = K (Vdd V)1 1 K OL n T 2 n ssuming that V = V = V V 0 K << K OL p n T Tn Tp p 2 +Vdd B C D Y 44/126

NMOS Logic Pseudo-NMOS VTC ( W/L n =1) 3.0 2.5 2.0 W/L p = 4 V out [V] 1.5 1.0 W/L p = 2 0.5 W/L p = 0.5 W/L p = 0.25 W/L p = 1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 45/126 V in [V]

NMOS Logic Improved Loads +Vdd +Vdd Enable M1 M2 M1>> M2 B C D Y 46/126

NMOS Logic Pseudo-NMOS Gates Design for unit current on output PMOS fights NMOS inputs f Y 47/126

NMOS Logic Pseudo-NMOS Power Pseudo-NMOS draws power whenever Y = 0 Called static power P = I VDD few m / gate * 1M gates would be a problem This is why NMOS went extinct! Use Pseudo-NMOS sparingly for wide NORs Turn off PMOS when not in use en B C Y 48/126

NMOS Logic Pseudo-NMOS ( NND) Layout Example Out In1 In2 In3 In4 49/126

Static CMOS Logic Family ll of the circuits described in the previous sections have a large static power dissipation. This disadvantage can be overcome by using Static CMOS Logic Family 51/126

Static CMOS Logic Family NOT +Vdd Vi M2 M1 Vo 53/126

Static CMOS Logic Family P/N ratio is normally selected for unit rise and fall resistance lternative: choose ratio for least average delay Only improves average delay slightly for inverters But significantly decreases area and power t = K(P+ 1) pdf t = K(P+ 1)( µ P) pdr t = K(P+ 1)(1+µ P) 2 pd dt pd dp = 0 P = µ 2 3 Least Delay Vi +Vdd P Vo 1 54/126

Static CMOS Logic Family Two inputs NND +Vdd M3 M4 Y B M2 M1 56/126

Static CMOS Logic Family Two inputs NOR +Vdd B Y 58/126

Static CMOS Logic Family NND is more suitable for CMOS because by suppose the equal W/L for NMOS and PMOS transistors, the PMOS transistor has more resistance respect to NMOS, therefore it is better to design circuit by paralleling the PMOS and cascading the NMOS The better Technology for digital circuit is N-Well, because in this Technology the NMOS transistors are made in the Sub. Which result better characteristic for transistor 59/126

Realization of More Complicated Gate Circuits a) Y = (B+C) It can be implemented in three levels: Gate Level Transistor Level Layout Level 61/126

Realization of More Complicated Gate Circuits a) Y = (B+C) Gate Level It consists of 10 transistors, 4 transistors for NOR, 2 for NOT and 4 for NND B C Y 62/126

Realization of More Complicated Gate Circuits a) Y = (B+C) Transistor Level It need only 6 transistors B +Vdd C Y B C 63/126

Realization of More Complicated Gate Circuits a) Y = (B+C) Layout Level By proper construction of layout, the parasitic capacitors are also reduced and area can be saved 64/126

Realization of More Complicated Gate Circuits b) XNOR (Y = B + B) Gate Level 16 transistors are needed Y B 65/126

Realization of More Complicated Gate Circuits b) XNOR (Y = B + B) Transistor Level (1)» How many transistors are» needed? +Vdd B B Y = B+ B B B 66/126

Realization of More Complicated Gate Circuits b) XNOR Transistor Level (2) Previous circuit can be simplified by eliminating two wiring lines +Vdd B B Y = B+ B B B 67/126

Realization of More Complicated Gate Circuits b) XNOR Transistor Level (3) In this circuit we have static power dissipation in the state of (=0,B=1) or (=1,B=0) +Vdd M3 Y = B+ B M1 M2 B 68/126

Realization of More Complicated Gate Circuits b) XNOR Transistor Level (4) (For less dissipation) Note to the state of = B = Vdd B Y +Vdd 0 0 0 Vdd Vdd 0 M4 M3 Y = B+ B Vdd 0 0 M1 M2 Vdd Vdd Vdd-Vth B 69/126

Realization of More Complicated Gate Circuits c) XOR s Previous the Source and Drain of M3 (or M4) are replaced by each other in different states, for example in state of =0, B=0 the b connection of M3 is Source B Y + Vdd 0 0 Vdd Vdd 0 Vdd 0 Vdd Vth Vdd-Vth Vdd 0 M2 M1 B a M3 b a M4 b Y = B+ B 70/126

Realization of More Complicated Gate Circuits d) Tri-State Outputs floating state at the output is needed Non-Inverting En = 1 Y = D En = 0 Y = Hi Z En +Vdd D En Y D Y 71/126

Realization of More Complicated Gate Circuits d) Tri-State Outputs floating state at the output is needed Inverting En = 1 Y = Hi Z En = 0 Y = D D Y En En +Vdd Y D 72/126

Realization of More Complicated Gate Circuits e) Schmitt Trigger M3 and M6 have minimum sized geometries With Vin = 0, the transistors M1 and M2 will be on but conducting negligible Drain current since M4 and M5 are off Vin Vx Vy +Vdd M1 M3 M2 Y Vy Vx Vdd M4 Vy Vdd M6 on Vz = Vy V TN Vz M6 M5 +Vdd 73/126

Realization of More Complicated Gate Circuits e) Schmitt Trigger When Vin rise to V TN, M5 turns on, but M4 is off. M5 and M6 form an NMOS amplifier. Thus as Vin rises, Vz is falling and in the certain voltage M4 turns on. With both M4 and M5 conducting, Vy rapidly goes to zero turning off M6. With Vy=0, M3 turns on, which aids in turning off M2 as Vx goes from Vdd to Vy-V TP s Vin decrease from Vdd to zero the operation is essentially similar. But now M1 turns on, in different voltage and Vin Vx Vy Vz +Vdd M1 M3 M2 M4 M6 M5 Y +Vdd 74/126

Transmission Gates Family Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates N transistors instead of 2N No static power consumption Ratioless Bidirectional 76/126

Transmission Gates Family NMOS Only Switch Vdd X In 3.0 In Voltage [V] 2.0 1.0 Out x 78/126 0.0 0 0.5 1 1.5 2 Time [ns]

Transmission Gates Family NMOS Only Switch V B does not pull up to 2.5V, but 2.5-V TN Threshold voltage loss causes (M 2 may be weakly conducting forming a path from Vdd to GND) NMOS has higher threshold than PMOS (body effect) 79/126

Transmission Gates Family NMOS Only Switch Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins 80/126

Transmission Gates Family NMOS Only Switch Solution1: Level Restoring Transistor Level Restorer B V dd M r V dd M 2 M n X Out M 1 81/126

Transmission Gates Family NMOS Only Switch Solution1: Level Restoring Transistor dvantages Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high Restorer adds capacitance, takes away pull down current at X For correct operation Mr must be sized correctly (ratioed) 82/126

Transmission Gates Family NMOS Only Switch Solution2: Multiple V T Transistors 83/126

Transmission Gates Family NMOS Only Switch Solution2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMOS TGs to eliminate most of the threshold drop (body effect still in force preventing full swing to Vdd) Impacts static power consumption due to subthreshold currents flowing through the TGs (even if VGS is below V T ) In 2 = 0V = 2.5V on low V T transistors Out In 1 = 2.5V off but leaking B= 0V sneak path 84/126

Transmission Gates Family NMOS Only Switch Disadvantage: It can be bad because the signal can be degraded We do not allow a few gates in series for one signal (Pure TG logic is not regenerative, the signal gradually degrades after passing through a number of TGs) dvantage: llow us to save transistor or less stage of logic 85/126

CMOS Transmission Gates Family PMOS Y C CMOS C C Y Y C C 87/126

CMOS Transmission Gates Family There are many symbols for transmission gate Be careful, because it is bi-directional 88/126

CMOS Transmission Gates Family This circuit performs a function similar to that of the well known diode bridge C= Vdd, C= 0 Both transistor are on = Y The input voltage V (which must be between Vss and Vdd) is then connected to the output through the parallel on resistance of the channels of the two transistors. s V approaches Vdd, the N-channel device cuts off but the P-channel device remains non saturated, as V approaches Vss, the P- channel device cuts off but the N-channel device remains non saturated. Therefore there is always a non saturated transistor between input and output C C Y Y C C 89/126

CMOS Transmission Gates Family For more understanding note to this circuit We assume: Vy(0 ) = 0, C= Vdd, C= 0, V < Vdd V TP TN V C Vdd Vy S D I P I N Y CL t C 90/126

CMOS Transmission Gates Family N = sat 0 t t I I I Vy= V = + TP P = sat CL N P N = sat t t t rcl Vy= V P TP Vy= Vdd V τ TN P = triode N = off t t t rcl Vy= Vdd V P TN Vy= Vdd τ P = triode C I P I N C Y CL 91/126

CMOS Transmission Gates Family It is normally assumed as a resistor V(t) = Vddu(t) C t Vy(t) = Vdd1 exp u(t) τtg τ = R CL TG TG R = r r TG N P I P I N C Y CL 92/126

CMOS Transmission Gates Family r N and r P are approximately as follow (In saturation region) r r N N 2 N(Vdd V TN ) P P 2 P(Vdd V TP ) β β 2V 2V V is Early Voltage R rp VTP RTG = rn rp r N Vdd V TN Vdd Vy 93/126

CMOS Transmission Gates Family What to note about TG The inputs must be able to give high current because they are connected directly to Drain and Source of transistors Since each input is connected to an RC circuit, The delay can be considered directly Limited Fan-in Excessive Fan-out Noise vulnerability (not restoring) Supply voltage offset/bias vulnerability Poor high voltage levels if NMOS-only Body effect 94/126

CMOS Transmission Gates Family Rules of Thumb Pass-Logic may consume half the power of static logic. But be careful of V T drop resulting in static leakage Pass-Gate Logic is not appropriate when long interconnects separate logic stages or when circuits have high Fan-out load (use buffering) 95/126

CMOS Transmission Gates Family ND 96/126

CMOS Transmission Gates Family OR Y = + B = (+ )(+ B) = + B B B Y Wired OR 97/126

CMOS Transmission Gates Family MUX S= 1 Y = B S= 0 S B S Y S 98/126

CMOS Transmission Gates Family MUX S S F F = (In1S+ In2S) V dd GND 99/126 In 1 S S In 2

CMOS Transmission Gates Family XOR B B Y = B B 100/126

CMOS Transmission Gates Family XNOR B B Y = B+ B B 101/126

CMOS Transmission Gates Family D Latch 1) Load Q = D 2) Hold Q = Q n n n n-1 D LD Q Q LD D LD LD Q LD 102/126

CMOS Transmission Gates Family D Latch 1) Load LD= 1 D Q= D D = Q 2) Hold LD= 0 Q Q 103/126

CMOS Transmission Gates Family D Latch (Simpler Realization) If in Load Mode a level voltage opposite to the output of weak inverter is applied to the input by TG, Q = D and weak inverter is not damaged! LD D Q LD Q Weak Inverter 104/126

Delay in Transmission Gate In V1 V2 Vi V i + 1 V n 1 C C C C C C V n In R eq R V eq 1 V2 R eq V eq eq i V i + 1 V n 1 C C C C C C R R R eq V n In m R eq R eq R eq R eq R eq R eq C C C C C C 105/126

Delay Optimization Delay of RC chain n t = 0.69 CR k = 0.69CR P eq eq k= 1 Delay of Buffered chain n(n+ 1) 2 n m(m+ 1) n t = 0.69 CR + 1 t m 2 m P eq buf n(m+ 1) n = 0.69CReq + 1 t 2 m Pbuf mopt = 1.7 CR eq t buf 106/126

TG Points to Remember Stored charge leaks away due to reverse-bias leakage current Stored value is good for about 1 ms Value must be rewritten to be valid If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid Capacitance comes primarily from inverter s gate logic 107/126

TG Layout 108/126

TG Properties Strong pull-up Strong pull-down May be difficult to design into a circuit (layout) because of close proximity of N and P devices (design rule separation) lways requires 2N transisitors for any N x TG design Many logic functions (multiplexers in particular) are easily implemented using TG based designs 109/126

Complementary Pass-transistor Logic (CPL) or Differential (+) TG Logic Dual-rail form of pass transistor logic voids need for ratioed feedback B B B B PT Network Inverse PT Network F F F F B B S S S S L L Y Y 110/126

CPL B B B B B F=B+BB F=B F= B B ND/NND F=B+B F=B F= B XOR/XNOR 111/126

4 Input NND in CPL Y Y X Y X Y OUT OUT 112/126

CPL dvantages Differential so complementary data inputs and outputs are always available (so don t need extra inverters) Still static, since the output defining nodes are always tied to Vdd or GND through a low resistance path Design is modular, all gates use the same topology, only the inputs are permuted Simple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) 113/126

CPL Disadvantages dditional routing overhead for complementary signals Still have static power dissipation problems V OH is very weak! Then we need an inverter at the output 114/126

Differential Cascode Voltage Switch Logic (DCVSL) Compute both true and complementary outputs using a pair of complementary NMOS pull-down network The PMOS transistors are driven by the output of the complementary network No static power consumption Fast response Y Y Inputs f f 116/126

Differential Cascode Voltage Switch Logic (DCVSL) Example: NND/ND Y = B Y = + B B Series B 117/126

LECTURE 9 : MOS Logic 118/126 Differential Cascode Voltage Switch Logic (DCVSL) General Design 1 1 1 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 F C B CMOS Logic + + + + + + + _ B C 0 1

Differential Cascode Voltage Switch Logic (DCVSL) General Design a b a b x _ + x x x _ + u u = ax+ bx u u u a b a b a b x _ + _ + x _ + u 1 u 2 u 1 u 2 119/126

Differential Cascode Voltage Switch Logic (DCVSL) General Design 0 1 C 0 1 _ + _ + _ + _ + C _ + _ + B _ + _ + _ + B _ + + + 120/126

Differential Cascode Voltage Switch Logic (DCVSL) General Design o 1 C C C C B B B B 121/126

Differential Cascode Voltage Switch Logic (DCVSL) Example: XOR/XNOR 122/126

Rules of Thumb Step-up (alpha) ratio of 2.7 ( e ) produces minimum powerdelay product P vs. N (beta) ratio of 2 balances pull-up and pull-down times and noise margins pproximately 75% of static logic are NND stacks (limit stack to 3-4, use ordering and tapering for speed) Glitches consume approximately 15% of overall chip power Crossover (short-circuit) current consumes ~ 10% of a static chip s total power (but is a function of input/output slews, ie sizing) 124/126

Summary This lecture describes the basic MOS Logic Gates which require no clock or other periodic signal for operation and also implementation of them in three following levels Gate Level Transistor level Layout Level 126/126