SCALING of CMOS technologies has defied all predictions

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 1023 The Impact of Scaling Down to Deep Submicron on CMOS RF Circuits Qiuting Huang, Senior Member, IEEE, Francesco Piazza, Paolo Orsatti, and Tatsuya Ohguro Abstract Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deepsubmicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-m CMOS appears to be the threshold for robust, low-nf RF front ends with current consumption competitive with today s BJT implementations. Index Terms CMOS RF, low-noise amplifier, low-power design, mixer, prescaler, RF-IC, technology scaling, wireless communication. I. INTRODUCTION SCALING of CMOS technologies has defied all predictions of technology limitations, and continues unabatedly toward the deep-submicron minimum feature size. This not only promises gigabit integration, gigahertz clock rate, and systems on a chip, but also arouses great expectations for CMOS RF circuits at 1 2 GHz, where the dominant technology is currently silicon bipolar. Various CMOS RF chips have been implemented in the last few years, with the ultimate goal of integrating a radio transceiver on a single CMOS chip [1], [2]. The successful inroads of CMOS into selective RF applications such as campus-wide wireless LAN and cordless phones naturally lead to the question of whether deep submicron CMOS could also be used for other more stringent applications. Examples of such more demanding applications include GSM handset and very low power pagers, etc. It is the purpose of this contribution to illustrate the device parameter improvements that can be expected as CMOS scales toward deep submicron, and to describe the significance of such improvements to key RF design parameters and building blocks. For RF designs, the achievable performance depends both on a transistor s transconductance coefficient and capacitances. The transconductance coefficient determines the amount of current required for a given gain and noise figure at the desired RF frequency. Both are critical for portable wireless Manuscript received November 26, 1997; revised February 9, 1998. Q. Huang, F. Piazza, and P. Orsatti are with the Integrated Systems Laboratory, Swiss Federal Institute of Technology, CH-8092 Zürich, Switzerland. T. Ohguro is with Toshiba Corporation, Tokyo, Japan. Publisher Item Identifier S 0018-9200(98)03432-5. applications, and tend to be high for CMOS implementations. The parasitic capacitances, on the other hand, limit the speed, have a strong influence on the achievable quality factor of resonant structures found in matching networks and oscillators, and often form undesirable coupling paths which reduce the achievable isolation between different circuit nodes. The miniaturization of CMOS transistors, driven primarily by digital applications so far, follows the primary objective of increasing circuit speed and density, both of which benefit from reduced channel length. In the submicron era, the primary obstacles from the device design viewpoint include such shortchannel effects as punchthrough and hot-electron degradation [3] [6]. The approaches that different manufacturers employ to scale down gate length may differ, but they generally require scaling down of oxide thickness, reducing junction depths, and increasing the channel (substrate) doping. As a result, both the transconductance coefficient and parasitic capacitances increase. Since two-dimensional effects, subthreshold turn-off behavior, and the pressure to maintain constant supply voltage force manufacturers to abandon simple scaling rules such as electrostatic scaling in the submicron era [3], [4], and since the exact approaches of different manufacturers to submicron scaling are often closely guarded secrets, discussion of scaling trend also becomes more difficult. Instead of assuming specific scaling rules, which may not even be followed by the same company in its different generations of CMOS, we adopt an empirical approach here, and examine the key process parameters, relevant to RF design, of a set of known submicron technologies over the last four to five generations. The discussion of MOS parameters in the following section will then be followed by discussions of how the four critical building blocks working at the highest frequencies in an RF front end will be affected by scaling before the general conclusions. The four RF front-end blocks to be discussed are the low noise amplifier (LNA), the mixer, the local oscillator (LO), and the frequency prescaler. Some experimental examples of LNA, mixer, and LO will be shown. II. ACTUAL TREND OF MOS PARAMETERS RELEVANT TO RF DESIGN Oxide thickness is an important parameter as it determines the unit gate capacitance, affects the threshold voltage, and has a strong influence on such short-channel effects as punchthrough, drain-induced barrier lowering, and gateinduced drain leakage. In the last few generations at least, oxide thickness has scaled down linearly with gate length. 0018 9200/98$10.00 1998 IEEE

1024 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 Fig. 1. Effective transconductance coefficient at 200 mv gate overdrive. Fig. 2. Gate and overlap capacitances per micron of gate width versus minimum channel length (transistor assumed in saturation region). The ratio between minimum gate length and oxide thickness is between 40 and 50 for different technologies. Since mobility at low field is a weak function of doping concentration [7], the transistor s transconductance coefficient at low field should scale inversely with the oxide thickness, and hence channel length, as shown by the dashed curve in Fig. 1. In analog and RF designs, however, input transistors are usually biased at 200 300 mv of gate overdrive. The drain source bias voltage is also usually much lower than the supply voltage, and remains constant for similar applications, relatively independent of process scaling. Since the reduction of oxide thickness and channel length exacerbates mobility degradation due to both the vertical and lateral field, the improvement of effective transconductance coefficient is much slower, as shown by the solid curve in Fig. 1. It can therefore be concluded that improvement in transconductance for the same current and ratio is much slower than the feature size reduction. Since RF circuits are usually small compared to both bonding pads and other baseband and digital circuits that may be integrated on the same chip, silicon area is usually not a primary concern. If the width of the transistor does not scale down as fast as the length, then transconductance does improve further for the same current. To what extent width

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1025 Fig. 3. Junction capacitance for the bottom of drain and source. can be maintained as technology scales down depends on the capacitances associated with the transistor. In RF circuits, critical transistors are invariably minimum length transistors, so that it makes sense to discuss the contribution of gate oxide to the transistor s input capacitance in terms of gate capacitance per micrometer of gate width, assuming that the length is set to the minimum for the technology. Fig. 2 shows both the gate source capacitance and the overlap capacitance between the gate and drain (source) per micron of gate width. The top half of the figure shows that the gate source capacitance for minimum length transistors stays more or less constant in the submicron era, reflecting the fact that oxide thickness scales more or less linearly with gate length. More remarkable is the bottom half of the figure, showing that the overlap capacitance remains roughly constant despite the fact that gate oxide scales down in each generation. (The authors have some doubts about the integrity of the measurements by the manufacturer of the two points marked with question marks.) This may be a demonstration that improved processing quality reduces the gate drain overlap. Shallower junctions and refinement in rapid thermal processing both seem to be favorable to reducing the lateral diffusion of the LDD implant into the channel area. If we assume that the voltage gain between the transistor s gate and drain is 1, as may be the case for an input transistor in a cascode configuration, then the equivalent capacitance seen into the gate node of the transistor is roughly 2 ff/ m, taking into account both gate source and gate drain overlap capacitances as well as the Miller effect. Although the variation of each actual technology from this average can be as much as 0.5 ff/ m, the constant average will be a useful concept for predicting performance for RF circuits, and will provide a benchmark for the quality of each individual process. The scaling trend for junction capacitances is more difficult to establish. There appear to be quite different attitudes toward both junction capacitances per unit area and per gate width from different companies. The scaling of gate length is also not always accompanied by the same effort to scale the minimum drain (source) width that covers one row of contacts. Fig. 3 shows the unit capacitance for the bottom of the drain and source junctions for two groups of companies. Fig. 4, on the other hand, shows the sidewall capacitances for the same companies. In Fig. 3, we see the lower points rising until the 0.35- m generation, reflecting the increase in channel, bulk, as well as drain/source doping concentration which is necessary to maintain low series resistance despite the decrease in junction depth. The same trend is also seen in the sidewall capacitances in Fig. 4. At 0.25 m, the bottom capacitance of one company and sidewall capacitance of another exhibit a sudden break from the upward trend, indicating that special processing measures are being taken to reduce the drain capacitance. Since 0.25- m technologies are not yet fully qualified for circuits at the time of this writing for most companies, it is difficult to predict if we will see an improving trend from 0.25 m on. We suspect that cost will make manufacturers limit their countermeasures to stopping junction capacitances from rising further. It is difficult to imagine a trend of these capacitances scaling down with channel length. In RF designs, noise is very important. The series gate, source, and drain resistances are therefore more important than ever. Silicided gate and drain/source are already widespread, however, so that such series resistances can be made negligible in the low gigahertz range by proper layout. III. GENERAL OBJECTIVES IN RF-IC DESIGN Radio frequency integrated circuit design for wireless communication is a complex subject, not only because the operating frequencies of 1 2 GHz are high for most silicon technologies. The radio front end is the part of a very complex system whose design is most affected by the radio network environment. In addition to the RF IC s, many passive com-

1026 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 Fig. 4. Sidewall capacitance versus minimum channel length. ponents are used in a transceiver for any of the following reasons: to select the desired radio channels and reject strong, out-of-band signals; to minimize the noise contribution from the image frequency; to provide impedance matching to board level transmission lines leading to high-frequency filters; to attenuate fluctuations of reference voltages and power supplies; to minimize undesirable signal feedthrough; to provide resonant structures for low-noise timing reference. The values of many passive components need to be tuned in production for the critical parts of the transceiver. The main objectives of RF-IC design, in addition to realizing functions that cannot be realized by passive components, are to achieve performances that enable unnecessary passive components to be eliminated, production tuning to be unnecessary, and cheaper components, especially filters, to be used so that the overall cost of producing the radio equipment is reduced. To appreciate the relative contributions to the overall cost, we note that manufacturing contributes 20%, filters and passive components contribute 5% each, and chipset, including baseband IC s, DSP, and controller chips, contributes 25% in a typical handset today [8]. There are only a few filters so that any circuit innovation that eliminates a filter or reduces its requirements will have a significant impact on cost. Passive components, on the other hand, are still found in today s handsets in the hundreds. Removing just a few of them may not make too much difference in overall cost. Removing those that require production tuning, however, removes an expensive part of manufacturing. In the design of the RF IC, it is therefore more important to make the circuit performance insensitive to the usual tolerances of passive components than integrating a few of them on chip. The smaller components used in the front end have higher tolerances, and are more susceptible to parasitics associated with board layout so that 10 20% errors should be expected. If the cost is critical to the profitability of a product, the performance-to-cost ratio is what makes it attractive to the users. In wireless applications such as cellular telephony, the speech quality is safeguarded by type-approval requirements so that the performance indicators visible to the users are usually talk/standby time, weight, and size. All three items are linked to the power consumption, which affects the requirements of the most expensive item in the handset (20%), the battery [8]. Of the total average power consumption of a typical receiver, 30 40% is consumed by the RF front end. Typical 900 MHz RF receiver chips integrated in advanced ( GHz) BJT technologies consume 50 ma in active mode [9] [11]. Integrated CMOS RF receivers published so far, on the other hand, consume 60 100 ma [1], [2], [12] while achieving less good overall performance. Since doubling of the power consumption translates to significantly increased battery cost, weight, and size for the same talk/standby time, any saving due to cheaper CMOS technology and higher integration level is instantly lost to the increase in battery price. Since batteries typically contribute to 20% of the overall handset cost, it is not difficult to see that CMOS will only become competitive if it can deliver power consumptions comparable to BJT implementations. The main design objectives of RF ICs can thus be summarized as the following. 1) Reach or exceed type-approval performance with the lowest power consumption to minimize battery cost, size, and weight.

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1027 2) Reach or exceed type-approval performance with the lowest number of tuned passive elements to minimize manufacturing cost. 3) Reach or exceed type-approval performance with the lowest number of external filters, as well as the minimum requirements for those filters at the highest frequencies. The latter include the RF filter (duplexer) and interstage image rejection filter, which tend to be large and expensive. Important active circuit parameters for type-approval performance include noise figure (NF), gain, small-signal linearity as described by intercept points ( ), large-signal linearity as described by a db compression point (CP), as well as reverse isolation as characterized by the scattering parameter. Phase noise is important at frequency offsets both within and exceeding the RF channel width. Within the RF channel, it degrades the signal-to-noise ratio. Outside the channel, it may reciprocal-mix out-of-band interefering signals onto the desired IF frequency. Most of our discussions will be based on receivers for more stringent requirements such as GSM, but will be independent of the receiver architecture, be it based on the superheterodyne or direct conversion principle. The only assumption in our discussion that may be more true for the case of superhet receivers than direct conversion receivers is the need for an interstage image-reject filter between the LNA and RF mixer. This external filter is usually required in high-performance receivers for two reasons. The first is to provide additional (to the RF filter before the LNA) attenuation for the strong, outof-band blocking signals before they reach the mixer, where intermodulation and reciprocal mixing issues are most critical. This attenuation is valuable for both superhet and direct conversion, especially for cellular applications such as GSM, where type approval requires the receiver to achieve a given bit-error rate in the presence of an interfering signal 20 MHz away and 98 db stronger than the signal in the desired channel. The second reason, valid for superhet receivers only, is to prevent noise at the image frequency prior to the mixer from being converted and superimposed on the same IF frequency as the desired channel. Without the filter, the overall noise figure referred to the LNA input can be up to 3 db higher. Because the filter has only limited attenuation at the image frequency and cannot suppress the mixer noise at the image, the actual improvement of overall NF is more like 1 2 db, depending on the relative noise levels of the LNA and the mixer [13]. In a very low-noise receiver such as GSM, however, 1 2 db NF degradation is unacceptable, and an interstage filter must be used. Bearing the above general objectives and requirements in mind, we are now in a position to examine the impact of CMOS scaling on each of the four RF front-end circuits. IV. THE LOW NOISE AMPLIFIER (LNA) The LNA is the first active circuit in the receiver chain, interfacing the duplexer or RF filter on the input side and either the image-reject interstage filter or the RF mixer directly on the output side. The most important requirements for the LNA are the following. 1) Provide sufficient gain so as to minimize the influence of noise contribution from building blocks after the LNA. The gain must not be too high, however, otherwise, large interfering signals, which have not yet been removed by channel filters, will exceed the limit that can be handled by the mixer s linearity. Typically, the LNA gain is between 12 20 db as a reasonable compromise. 2) Contribute as little noise as possible. The required noise figure may differ from application to application. For stringent applications such as GSM, the LNA noise figure needs to be below 2 db because unavoidable losses of various filters leave very little noise budget for the active circuits. This is quite hard to achieve even with BJT implementations, and in some systems, the LNA is still constructed off chip with external discrete transistors and passive components. 3) Provide 50- interface to the RF filters at both the input and the output, with the help of as few external conponents as possible. The overall gain should be insensitive to tolerances of typical external components, and production tuning of such components should be avoided. 4) Provide sufficient small-signal linearity at the input and large-signal linearity at the output. The latter requirement, measured in terms of 1 db compression point, can be as high as 0 dbm at the LNA output, which places a lower limit on the current that must be provided by the output stage. There are essentially two ways of configuring the input transistor for an LNA: common-gate ( - ) as shown in Fig. 5(a) and common-source ( - ) as in Fig. 5(b). Also shown are the possible external components for impedance matching. For applications that are more tolerant to LNA noise, the - configuration can sometimes be designed to provide 50- input resistance without any external matching components [14]. The drawback of the - configuration is that the theoretical minimum for achievable NF is 2.2 db. If one adds degradation due to the hot-electron effect and other parasitic noise sources such as pad and substrate resistances, the NF is more likely to be more than 3 db [14]. In a GSMlike application, such NF is too high. In this discussion, we concentrate on the - configuration, which is capable of lower NF. The definition of NF itself dictates a law of diminishing return, so that, although there does not seem to be much difference between 3 and 2 db NF, achieving the latter is considerably harder, and few CMOS LNA s have done so, even when high current is expended. The input impedance of the LNA is matched to the source resistance when the following conditions are met: (1) (2)

1028 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 Fig. 5. source. Input stage of low noise amplifier: (a) common gate and (b) common Under matching conditions, the overall transconductance from the input of the matching inductor to the drain of is given by, independent of the transconductance of. The voltage gain of the amplifier is determined by the product of this overall transconductance and the transimpedance of the output stage to be discussed later. The latter is on the order of 50 100 if the output stage is to interface to an external image-reject filter directly, without a matching network. To realize an overall gain of 15 db, the value of is then on the order of 1 2 nh at 1 GHz. This is the same range as that of a typical bonding wire, so that can be realized as a bondwire for 1-GHz RF applications, and the only external component in the input matching network of Fig. 5(b) is inductor. Between the input of the matching network and the gate source voltage of, there is a voltage gain equal to the quality factor of the second-order transfer function at the resonance frequency : This gain is important in scaling the influence of the transistor noise on the NF of the overall amplifier. For example, if only s drain current noise is taken into account, the amplifier NF is given by It is clear from both (3) and (4) that a higher is beneficial to both improving NF and reducing the required, and therefore current consumption. The use of a high- matching network, however, is limited by several considerations. One reason is that a high- network results in large reactance levels associated with and compared to the real part of the input impedance which is 50. Although the nominal capacitive and inductive reactances cancel each other, 10 20% tolerance in their values results in a larger deviation for higher from the ideal 50- one wishes to realize. The 50- termination is required primarily by the RF filter, which is doubly terminated for maximum power transfer and lowest sensitivity. The specifications for the RF filter, such as insertion loss, passband ripple, and stopband attenuation, are only guaranteed for a given tolerance in terminating impedance, between 25 and 100, for example. When the impedance level exceeds such limits, the conditions for which the filter has low sensitivities are no longer maintained, and the passband ripples, as well as the stopband attenuation, may worsen due to parameter tolerances. Fig. 6 shows that the (3) (4) Fig. 6. Passpand insertion loss of the Rx path of a commercial duplexer for GSM, Murata DFY2R902CR947BHGF. The solid curve is measured with filter output terminated with 50- impedance. The dashed curves are measured with the output terminated with impedances having s11 = 06 db, 45 in each quadrant of the Smith chart. measured insertion loss of a commercial duplexer can already worsen by more than 0.5 db if the of the termination impedance is 6 db. This means that the precious NF before the LNA can worsen by the same amount, which incurs a very serious penalty. It is therefore our opinion that while a of 2 3 can be beneficial for reducing the LNA current consumption and NF, it should not exceed 5 to avoid the necessity to tune. Tuning, as we stated earlier, increases the manufacturing cost that is already a high percentage of the overall handset cost. A survey of commercial LNA and RF chips by well-known manufacturers shows a dwindling number of trimmed high- matching networks. The (loaded) is indeed below 3 in all of the untrimmed matching networks we found in data sheets and application notes [15]. For the purpose of discussing scaling, it is also important to fix to a common value so that performance improvement due to process parameter improvements can be better appreciated. In the following, we assume that the LNA matching network is designed to have a of 2.5, but the active part is implemented in different generations of technologies. We also assume that the RF frequency remains at 1 GHz, and we examine the effect of scaling on required current consumption. Once the matching network is fixed, so is the gate capacitance of. Rearranging (3) and (4), we have pf (5) where GHz, and. According to our discussion in the earlier section on CMOS scaling, the gate capacitance per micron width is roughly constant and is given by ff/ m (6) where the gain for the Miller capacitance is assumed to be. To satisfy the condition in (5), the required gate width

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1029 Fig. 7. Required bias current for 60-mS transconductance versus channel length channel width is 600 m. Fig. 8. Low-noise amplifier schematic. is on the order of 600 m, as long as the technology scaling follows the trend in Fig. 2. The required transconductance to meet the matching condition (3), on the other hand, is also fixed once is decided and the required bondwire inductance is known. For and nh, is on the order of 60 ms. Assuming a simple quadratic characteristic for, the required first-stage current for different generations of CMOS can be estimated: ms m This current is plotted in Fig. 7 versus five different feature sizes using the data from Fig. 1. Similar curves can be plotted for higher or lower, but the trend will be similar. For, we see that at 0.8 m, the required current is nearly 25 ma for the first stage alone. For 0.5- m CMOS, the current reduces to 12 ma. Better current consumption can be achieved with higher, as shown in [16]. The price paid there, however, is a 6-dB variability in LNA gain for a 10% shift in center frequency. At 0.25 m, the current for the first stage drops to 4 ma. Since MOS transistors always have a lower -to-current ratio than bipolar transistors, this current (7) Fig. 9. Photomicrograph of the 0.25-m CMOS LNA. consumption is still inferior to some of the state-of-the-art BJT designs for comparable specifications (2.5 ma in [17]). The gap, however, is sufficiently small for CMOS to challenge BJT at 1 GHz on the strength of lower cost. One of the well-established ways of realizing the output stage of the LNA is the transimpedance structure (, and ) shown in Fig. 8 [17], [18]. The main design issues here are to: direct most of the signal current from the input stage to the feedback resistance (50 100 ) to realize the overall gain of 12 20 db; present the output of the first stage a sufficiently low input resistance so that the dominant pole it forms with the parasitic capacitances (junction and overlap capacitances of the input cascode transistor plus the gate capacitance

1030 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 Fig. 10. Measured LNA gain and noise figure. of ) is sufficiently high compared to the signal frequency; this requires a high for to achieve high loop gain for the transimpedance stage; provide sufficient output current to fulfill linearity requirements such as and especially output ; combine the values of, and especially of in such a way that the output resistance of the LNA is close to 50 to allow direct impedance matching to the interstage image-reject filter without external components. One alternative to using the transimpedance output stage is to use on-chip spiral inductors to tune out the parasitic output capacitance of the first stage so that high gain can be realized. A buffer can then be used to provide 50- matching and isolate the high gain stage. With the help of on-chip inductors, bias current of the input stage can be reused by the buffer stage, so that the overall current consumption remains low [19]. One of the drawbacks of such a solution, however, is that the gain of the LNA is defined by (the of) a resonator formed by a spiral inductor and parasitic capacitors. The resonator is in turn defined by parasitics such as interconnect metal resistance and substrate loss, as well as the output resistance of cascoded transistors, which all have strong variability. Together with the variability of the resonant frequency itself, the overall gain may vary beyond the limits acceptable for high yield production, and cannot even be tuned. Returning to the transimpedance output stage in Fig. 8, the tradeoffs in the requirements listed above confine the of to about 50 ms, which cannot be realized as a wide and low current combination. The primary limitations are the contribution of s gate capacitance to the cutoff frequency and linearity of the LNA. The pole associated with the drain of the input stage limits the width of to the same order of magnitude as that of. For channel lengths above 0.5 Fig. 11. Schematic diagram of a double-balanced mixer. m, the trend in current consumption shown in Fig. 7 will be repeated for the output stage. Below 0.35 m, however, further reduction of current is prevented by the linearity requirement. The linearity of the output stage is especially dictated by the output compression point requirement which is on the order of 0 dbm, for a cellular phone environment typically characterized by a minimum input signal strength of 110 to 100 dbm and a signal dynamic range of 90 100 db [20]. Without a matching network, the output transistor sees the 50- input resistance of the image-reject filter, in parallel with the bias and feedback resistances of the LNA. Even if the latter resistances are made large so that the 50- load resistance dominates, the minimum peak output current required to achieve 0 dbm ( 300-mV peak) is 6 ma. This value is independent of the active device, so that scaling beyond 0.35 m is unlikely to have a significant influence on this part of the current consumption. Indeed, a similar current consumption of 5.5 ma was used even in the BJT solution in [17]. To summarize the discussions on LNA, we can state that for the same application frequency of 1 GHz, the bias current

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1031 TABLE I SUMMARY OF LNA MEASUREMENTS of the input stage will scale slightly faster than the feature size reduction of the technology. The output current, on the other hand, scales down until it reaches 5 6 ma, where it will remain constant. For a current consumption close to state-ofthe-art BJT implementations, 0.25- m CMOS is necessary for comparable performance. To demonstrate the overall performance achievable by a 0.25- m CMOS technology, we developed a prototype LNA circuit based on Fig. 8 and the discussions above. The measured performance is summarized in Table I, whereas the die photo is shown in Fig. 9. Worth noting is the noise figure of 1.85 db, which is the lowest reported so far in the literature for CMOS IC s. The total current consumption, 10.8 ma, is very close to state-of-the-art BJT implementations [17], [21]. Fig. 10 shows the measured and NF versus frequency. Both are very flat, demonstrating the advantage of a lowdesign. V. THE MIXER In addition to the obvious function of frequency translation, the desired characteristics of a mixer include the following: low-noise figure ( 15 db); a moderate conversion gain to reduce the noise contribution of the IF or baseband amplifiers to the overall NF; high linearity; 50 input impedance (to match to the interstage image reject filter); low coupling from the LO to the RF port; suppression of LO feedthrough to the IF port (if passive IF filter is absent). Although many mixer structures exist [22] and some new ones have recently been proposed, the only configuration that fulfills most of the requirements at 1 2 GHz, especially the first two listed above, is the well-known Gilbert mixer, whose simplified diagram is shown in Fig. 11. It is essentially a transconductance stage followed by commutating switches. The latter usually dominate the overall mixer noise figure, which typically lies around 15 db for BJT implementations at 1 GHz for a typical LO level of 0 dbm [9], [17]. For the input transconductance stage, much of the discussion about the LNA input stage is still valid. The common-gate input stage, however, is more acceptable in the mixer case because, whether the input transistor contributes 2 or 3 db to the overall noise figure, the difference is relatively small. The advantage of a - input, on the other hand, is that the of each input transistor can be set to 40 ms, so that the two input transistors provide a natural broad-band 50- matching. For a given input transconductance, the main limitation to improving current consumption is linearity. The RF signals reaching the mixer have already been filtered by the RF filter before the LNA and the interstage filter after the LNA, so that blocking signals far away from the block of channels assigned to the service (such as GSM) have already been attenuated. Within the service, however, the near far situation may still cause signals on other users channels to be much higher (30 db, for instance) than one s own. Indeed, GSM-type approval requirements stipulate that a receiver must be able to maintain a minimum BER when detecting a 98 dbm signal in the presence of two interfering signals 49 db (four channels away) and 48 db (eight channels away) higher, respectively. Such signals are amplified by the LNA, and reach the mixer without filtering so that the latter must have a high (and in the case of direct conversion). We will therefore concentrate our discussion of the mixer on the third-order intercept point. To obtain an estimate of, we describe the relationship of as in (8) [4]: where and (8) (9) (10) If we apply two signals of equal amplitude to the double-balanced mixer, each input transistor sees half of the input signals. Expanding (8) into a power series with equal to the sum of two sine waves with equal amplitude and collecting the third-order terms, it can be shown that the input-referred third-order intermodulation product for each transistor is given by (11) A single sine-wave input with the same power as the twotone test above has an amplitude. Equating with in (11), we obtain the third-order intercept point in dbm (the dimensions in the log terms cancel out in the algebraic sum): (12) If one maintains the same input (40 ms each transistor for 50- matching, for example) and the same (plus

1032 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 Fig. 12. Progression of IP3 and bias current for double-balanced mixer. the drain capacitance of the bias transistor and the input pad capacitance) for a given corner frequency, then the width of remains roughly the same as the technology scales. The resulting improvement in the ratio, although beneficial to current reduction in the same trend as shown in Fig. 7, degrades linearity, as indicated by (12). This degradation is exacerbated by the worsening of, which is believed to be inversely proportional to the oxide thickness [4], [7]. The parameter, or its equivalent in various SPICE models, is often not given enough attention by people who measure the transistor parameters, so that reliable measured data are hard to come by. The inverse proportionality of to oxide thickness, although not always corroborated by foundry data, gives us a reasonable indication of the impact of scaling on linearity, as long as the transistor works in strong inversion: (13) Fig. 13. Photomicrograph of the 0.25-m CMOS mixer. According to [4], the coefficient ( times the oxide thickness ) has a range of 1 4 nm/v. The value of 4 nm/v is used to generate Fig. 12, which shows that, for a given width of 400 m (corresponding to an input corner frequency of 4 GHz for a 0.25- m design), the required current to realize 40 ms for input matching scales down rapidly with decreasing channel length. According to (13), also degrades, at a rate slightly faster than the reduction of channel length. Similar conclusions have been drawn in [23]. If we compare the predicted by (13) at 1 m length and measurements in the literature, such as the reported in [14], the results are very close. The application of (13) to the 0.25- m technology assumes that the overdrive for transistor is more than 100 mv, still well above the subthreshold limit. The resulting ratio is about 13. Assuming a subthreshold slope of 1.5, the maximum ratio that can achieve is mv. TABLE II SUMMARY OF 0.25 m MIXER MEASUREMENTS This happens when the transistor works in weak inversion and (13) is no longer valid. A further reduction of current will result in rapid degradation in as the transistor assumes an exponential characteristic. The dashed line in Fig. 12 depicts

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1033 Fig. 14. Measurement of third-order intercept point for double-balanced mixer. the likely departure of the actual from that given by (13) and the rapid degradation of to bipolar levels. The for a bipolar transistor, based on the same definition as above, is 8.15 dbm. Because the subthreshold slope of a MOSFET lies between 1 and 2, the worst case for MOS is still better than the bipolar case. For a typical slope of 1.5, the is 5 dbm for weak inversion operation. This is far below the for a strong inversion operation as given by (12) or (13). Even for a 0.25- m implementation, measurement shows that the is 9 dbm, 9 db below the prediction by (13). This shows that the transition to bipolar behavior has already started at the level of 3 ma. If high linearity of the MOSFET has been assumed as a basis for a particular architecture or receiver plan, then strong inversion operation must be maintained, even if this means keeping the current constant and reducing the transistor width with the channel length. Returning to Fig. 12, we can conclude that current consumption reduces with scaling, reaching 3 ma (6 ma for the mixer) for 0.25- m technology. Such a current consumption is already sufficiently small compared to the overall current consumption of RF receivers today, so that substantial further reduction at the expense of drastic degradation in is unnecessary. Whether current reduction continues or levels out for future CMOS processes below 0.25 m depends on the influence of current on the mixer noise figure. Similar to the input transistors, the width of the switching transistors can be kept constant while the gate length, as well as current, scale down. The of the switching transistors will stay roughly unchanged, as does their drain noise current. The ratio between the switching transistor gate overdrive and the LO amplitude determines the time period in which both transistors in the source-coupled pair are conducting. During this period, the switching transistor contributes to the mixer noise figure substantially. Reducing the gate overdrive, as a result of the above scaling, reduces the duty cycle in which Fig. 15. Schematic diagram of Clapp oscillator. noise of the switching transistors is present, and improves the overall noise figure. To verify one s ability to provide 50- matching without external components, and to use low current while maintaining good mixer performance, we implemented a double-balanced mixer in a 0.25- m CMOS. Fig. 13 shows its photomicrograph. The mixer was designed for a 900-MHz, superhet GSM receiver. The measured parameters are summarized in Table II. Fig. 14 shows the measurement. Apart from 50 input without a matching network and the high and,a remarkable feature is the mixer s SSB noise figure of 12.8 db, which is better than many BJT realizations by 2 3 db [9], [17]. VI. THE LOCAL OSCILLATOR (LO) First-order oscillators such as ring and relaxation oscillators generally have too high phase noise to be useful in mobile receivers. This leaves -tuned oscillators, or those based on other resonators, to be the only type found in mobile phone handsets. The Clapp oscillator, shown in Fig. 15, is among the most widely used types, which we will use as example here. In a well-designed oscillator, the main active device (or devices in differential implementations), be it BJT or MOS, operates in Class-C mode like a switch. Upon triggering by

1034 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 the sine wave on the resonator, the active device injects impulses of current back into the resonator to sustain oscillation. Intuitively, therefore, once the transistor behaves like a switch, further decreasing the channel length will only have a limited impact on the oscillator performance. For an RF local oscillator, the most important parameters are LO amplitude, phase noise, and current consumption. The first two are closely linked with the third. For a single-ended Clapp oscillator, the oscillation amplitude is given by [24] (14) where is the resistive loss of the resonator, is the angular frequency of oscillation, and is the critical required of to start oscillation. The parameter is a function of the ratio between s nominal transconductance and. The range of is between and. In typical designs, the ratio is higher than 5 and, so that the influence of the transistor s dimensions on, and in turn, becomes very small. It can be shown that the ratio between the phase noise spectral density at an angular offset frequency from the oscillation and that of the carrier is given by (15) [25], [26]: (15) where is the quality factor of the resonator and is the transconductance of the bias transistor. Normally, capacitors and are set equal, so that the first term in the square brackets is the same as. Since increases the phase noise, it should be set to three five times to ensure that oscillation starts and is close to 1, but no more. Transconductance should also be minimized to the extent permitted by the voltage swing requirement of the bias transistor. If we assume the last term in the square brackets in (15) to be negligible compared to the first two, which are in turn determined by the parameters of the passive resonator, then the phase-noise-to-carrier ratio is more or less only determined by the bias current and the resonator. For a given resonator in the 1 2-GHz range, which is usually external and not affected by the active device, scaling does not improve the oscillator performance. There has been quite some effort in the IC community to incorporate spiral inductors on chip using interconnect metal layers. Remarkable progress has been made in the quality of such inductors [27], so that even the phase noise requirement for GSM applications, believed to be around 115 dbc/hz at 100-kHz offset, may be met in the future by such oscillators with a reasonable current consumption. From the point of view of technology scaling, as long as the number of interconnect metal layers stays the same (it has been two three layers for most technologies used for mixed-signal applications), then Fig. 16. Photomicrograph of 0.4-m CMOS Clapp oscillator (chip includes a 1-mA frequency prescaler). scaling has relatively little impact on parameters that may affect the spiral inductor quality. Many deep-submicron digital technologies are providing five layers of metal or more to ease the digital interconnect problem. In such technologies, the field oxide thickness between the top metal and the substrate increases, so that the achievable quality factor may also increase. In that case, current consumption in integrated spiral- oscillators will decrease. To demonstrate what is achievable, we implemented a 1-GHz Clapp oscillator a few years ago with an external resonator and an NMOS transistor 500 m wide and 1 m (minimum length) long. The current consumption was a little over 1 ma and the phase noise at 100-kHz offset was 113 dbc/hz. Recently, we implemented another Clapp oscillator in 0.4- m CMOS (micrograph shown in Fig. 16) [26] with a similar external resonator (except that the inductor is an SMD device rather than hand-wound). The current consumption stands at 1.5 ma, whereas the phase noise is still 113 dbc/hz at 100 khz, as shown in Fig. 17. In terms of phase noise per milliampere of current consumption, an external resonator is still 12 db better than the best fully integrated solutions at 1 GHz. It remains to be seen if this would be changed by increased metal layers in future generations of CMOS. VII. THE FREQUENCY PRESCALER The impact of scaling on digital circuits has been extensively studied in the past, and much better understood than analog functions. The discussion here is intended for completeness, and will be kept brief. The first observation to be made here is that inverter-based digital logic and flip-flops usually consume too much power at the gigahertz frequency range to be useful for RF applications. More importantly, such single-ended structures generate impulsive disturbances with frequency contents close to the LO and RF frequencies, which will be coupled to the signal path through the power supply and substrate. This makes them unacceptable to the RF front end. Prescalers in RF receivers are therefore almost exclusively implemented with emitter-coupled logic, or their CMOS counterpart, the enhancement source-coupled logic (ESCL), which generate fewer disturbances. Low power consumption is mainly a result of lower logic swing, the latter

HUANG et al.: SCALING DOWN TO DEEP SUBMICRON 1035 higher than unity (we take 2 to allow sufficient margin), and the appropriate logic swing. The latter must be sufficiently large to ensure operation, but not too large in order to save power. We take 200 mv as an appropriate level: (18) (19) Combining (16) (19), we can establish an estimate of the time constant as a function of transistor dimensions: (20) Fig. 17. Measured output power spectrum of 900-MHz Clapp oscillator. As the channel lengths scale down and transconductance coefficients go somewhat up, can be scaled down faster than to maintain the time constant at the same level as before, until the minimum value allowed by the design rules is reached. The reduction of allows the bias current to be scaled faster than the channel length for the same operating frequency. (a) (b) Fig. 18. (a) ESCL inverter with PMOS load and (b) equivalent circuit with parasitics. being compatible with the signal level of its driver, the local oscillator. Earlier ESCL logic uses a diode-connected PMOS or NMOS transistor as the active load [28]. The voltage drop across the load transistor, however, makes it unsuitable for deepsubmicron CMOS because of the reduction. Folded source-coupled logic (FSCL) [29] is better for low-voltage operation, but has the drawback that current consumption is doubled for the same speed requirement. A better sourcecoupled logic structure is to use PMOS transistors biased in the triode region as the resistive load [30], [31], as shown in Fig. 18. The load resistance is determined by the bias voltage and the aspect ratio of the transistor: (16) The capacitance associated with the output node, which will limit speed and dictate the required current, consists of parts that scale with the width of the transistors and parts that are fixed, such as the sidewall capacitance along the two sides of the drain and wiring capacitance. (17) The important design considerations are the maximum time constant, minimum gain of the inverter, which must be VIII. CONCLUSIONS Radio frequency design for portable wireless applications is characterized by complex tradeoffs among system requirements, receiver architecture, passive off-chip components, and active circuits. In this contribution, the boundary conditions for the IC design are assumed to be such that the resulting solution is most robust to production tolerances and low cost in the overall sense, and meets stringent requirements of cellular phone systems such as GSM. Power (current) consumption receives particular attention because it affects the lifetime, size, and weight of the most expensive item in a handset, the battery. Within such boundary conditions, it is shown that LNA and mixer current consumptions need necessarily be high with CMOS feature sizes above 0.5 m. At 0.25- m channel length, the current consumption for both types of circuits come down to sufficiently low levels for CMOS to compete with BJT at 1 2 GHz on the strength of cost if deep-submicron CMOS is indeed cheaper than 15-GHz bipolar or BiCMOS technologies. Excellent performances have been achieved by the 0.25- m CMOS LNA and mixer presented in this paper. The performance of a local oscillator, usually implemented with a tuned resonator, is mainly determined by the bias current and the resonator, so that at 1 2 GHz, the impact of scaling is minor. The frequency prescaler, on the other hand, enjoys current reduction faster than channel length scaling, as do most digital circuits. REFERENCES [1] A. Abidi et al., The future of CMOS wireless transceivers, in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1997, pp. 118 119. [2] J. Rudell et al., A 1.9GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone applications, in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1997, pp. 304 305. [3] R. K. Watts, Ed., Submicron Integrated Circuits. New York: Wiley- Interscience, 1989.