Comparison of Power Dissipation in inverter using SVL Techniques

Similar documents
DESIGN AND ANALYSIS OF NAND GATE USING BODY BIASING TECHNIQUE

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique

Characterization of Variable Gate Oxide Thickness MOSFET with Non-Uniform Oxide Thicknesses for Sub-Threshold Leakage Current Reduction

CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES

Characterization of 6T CMOS SRAM in 65nm and 120nm Technology using Low power Techniques

Design of High Performance Arithmetic and Logic Circuits in DSM Technology

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010

A NEW APPROACH FOR DELAY AND LEAKAGE POWER REDUCTION IN CMOS VLSI CIRCUITS

UNIT-1 Fundamentals of Low Power VLSI Design

Sub-threshold Leakage Current Reduction Using Variable Gate Oxide Thickness (VGOT) MOSFET

Ultra Low Power VLSI Design: A Review

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

A Survey of the Low Power Design Techniques at the Circuit Level

Minimizing the Sub Threshold Leakage for High Performance CMOS Circuits Using Stacked Sleep Technique

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits

Variable Body Biasing Technique to Reduce Leakage Current in 4x4 DRAM in VLSI

A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design

Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages

Design Of Level Shifter By Using Multi Supply Voltage

Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique

Low Power Design of Successive Approximation Registers

Design Analysis of 1-bit Comparator using 45nm Technology

LEAKAGE POWER REDUCTION TECHNIQUES FOR LOW POWER VLSI DESIGN: A REVIEW PAPER

1. Introduction. Volume 6 Issue 6, June Licensed Under Creative Commons Attribution CC BY. Sumit Kumar Srivastava 1, Amit Kumar 2

DESIGNING OF SRAM USING LECTOR TECHNIQUE TO REDUCE LEAKAGE POWER

Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits using Modified Sleepy Keeper

A HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

Pramoda N V Department of Electronics and Communication Engineering, MCE Hassan Karnataka India

Design and Analysis of CMOS and Adiabatic logic using 1:16 Multiplexer and 16:1 Demultiplexer

Investigation on Performance of high speed CMOS Full adder Circuits

IJMIE Volume 2, Issue 3 ISSN:

Total reduction of leakage power through combined effect of Sleep stack and variable body biasing technique

High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach

Unique Journal of Engineering and Advanced Sciences Available online: Research Article

EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis

Leakage Power Reduction in CMOS VLSI Circuits

Low Power High Performance 10T Full Adder for Low Voltage CMOS Technology Using Dual Threshold Voltage

International Journal of Advanced Research in Biology Engineering Science and Technology (IJARBEST)

ESTIMATION OF LEAKAGE POWER IN CMOS DIGITAL CIRCUIT STACKS

COMPARISON AMONG DIFFERENT CMOS INVERTER WITH STACK KEEPER APPROACH IN VLSI DESIGN

EEC 118 Lecture #12: Dynamic Logic

Wide Fan-In Gates for Combinational Circuits Using CCD

LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Leakage Power Reduction by Using Sleep Methods

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection

Design & Simulation of Half Adder Circuit Using AVL technique based on CMOS Technology

International Journal of Innovative Research in Technology, Science and Engineering (IJIRTSE) Volume 1, Issue 1.

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for Sub-130nm CMOS Technologies

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Power-Area trade-off for Different CMOS Design Technologies

Novel Buffer Design for Low Power and Less Delay in 45nm and 90nm Technology

Study of Outpouring Power Diminution Technique in CMOS Circuits

Design of low power SRAM Cell with combined effect of sleep stack and variable body bias technique

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

STATIC POWER OPTIMIZATION USING DUAL SUB-THRESHOLD SUPPLY VOLTAGES IN DIGITAL CMOS VLSI CIRCUITS

ZIGZAG KEEPER: A NEW APPROACH FOR LOW POWER CMOS CIRCUIT

Comparison of Leakage Power Reduction Techniques in 65nm Technologies

3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE

EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders

Design and Analysis of Sram Cell for Reducing Leakage in Submicron Technologies Using Cadence Tool

A Novel Approach for High Speed and Low Power 4-Bit Multiplier

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Study and Analysis of CMOS Carry Look Ahead Adder with Leakage Power Reduction Approaches

Design and Optimization of Half Subtractor Circuits for Low-Voltage Low-Power Applications

A Case Study of Nanoscale FPGA Programmable Switches with Low Power

A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)

UNIT-III GATE LEVEL DESIGN

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

Leakage Power Reduction in CMOS VLSI

Leakage Current Analysis

A NOVEL 4-Bit ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

UNIT-II LOW POWER VLSI DESIGN APPROACHES

Design of a Low Voltage low Power Double tail comparator in 180nm cmos Technology

Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

Performance Analysis of Energy Efficient and Charge Recovery Adiabatic Techniques for Low Power Design

Contents 1 Introduction 2 MOS Fabrication Technology

Implementation of High Performance Carry Save Adder Using Domino Logic

EE 330 Lecture 44. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

Performance Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology

COMPREHENSIVE ANALYSIS OF ENHANCED CARRY-LOOK AHEAD ADDER USING DIFFERENT LOGIC STYLES

Low Power Design for Systems on a Chip. Tutorial Outline

Analysis of shift register using GDI AND gate and SSASPL using Multi Threshold CMOS technique in 22nm technology

Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc

Implementation of dual stack technique for reducing leakage and dynamic power

BASIC PHYSICAL DESIGN AN OVERVIEW The VLSI design flow for any IC design is as follows

Double Stage Domino Technique: Low- Power High-Speed Noise-tolerant Domino Circuit for Wide Fan-In Gates

Low Power, Area Efficient FinFET Circuit Design

MULTITHRESHOLD CMOS SLEEP STACK AND LOGIC STACK TECHNIQUE FOR DIGITAL CIRCUIT DESIGN

EE 330 Lecture 43. Digital Circuits. Other Logic Styles Dynamic Logic Circuits

Design of Low Power Vlsi Circuits Using Cascode Logic Style

4 principal of JNTU college of Eng., JNTUH, Kukatpally, Hyderabad, A.P, INDIA

Low-Power Digital CMOS Design: A Survey

Designing and Simulation of Full Adder Cell using Self Reverse Biasing Technique

Transcription:

Comparison of Power Dissipation in inverter using SVL Techniques K. Kalai Selvi Assistant Professor, Dept. of Electronics & Communication Engineering, Government College of Engineering, Tirunelveli, India ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - As technology scales the size of chip, leakage power has become a important component in chip design. Leakage power is an essential parameter to be taken into account while designing low power devices.large amount of leakage power is an serious & undesirable factor in portable electronics devices. High power consumption raises the cost and also reduces the battery life of the devices. So it is essential to reduce the dynamic as well as the static power consumption. Increasing the threshold voltage reduces the leakage power of the circuit. Low energy consumption in devices requires very low power circuits. This paper compares the inverter circuits i.e static CMOS inverter & Domino inverter with Upper & lower Self controllable Voltage Level (SVL). Power Consumption & power Dissipation of Upper SVL Domino circuit is found to be less. As power dissipation is reduced, consequently there must be a reduction in leakage power. All the simulations have been carried out in Microwind tool at 90 nm technology,vdd Supply of 1.2 volt is given, input sequence used is 01010.The other name of Self controllable Voltage Level is Adaptive voltage level circuit (AVL). Key Words: Static CMOS, USVL (upper selfcontrollable voltage level),lsvl (lower self controllable voltage level), Leakage current, Power dissipation. 1. INTRODUCTION The latest trends in VLSI technology needs a reduction in power supply voltage (Vdd) to reduce dynamic power in deep sub-micron (DSM) regimes. However, a reduction in Vdd decreases the threshold voltage (Vth). This reduction in Vth causes the leakage currents to increase exponentially and they become a important contributor to total power dissipation in VLSI chips. The subthreshold leakage current I leak is given by the expression I leak = I 0 exp[(vgs Vth)/nVT] --- (1) where I 0 = μ 0 C ox (W/L) V 2 e1.8, 1.1 DOMINO LOGIC Dynamic circuits such as domino logic circuits are used in high performance microprocessors for obtaining high speeds that are not possible with static CMOS circuits. Their high speed is due to reduced input capacitance, small switching thresholds and circuit implementations that typically use fewer levels of logic due to the usage of efficient and wide complex logic gates. But the penalty to be paid for speed improvement is the increased power dissipation, mainly due to the necessary clocking and increased noise sensitivity. Hence, this imposes the challenges in the design of dynamic circuits. 1.2. DOMINO INVERTER Domino style incorporates clk inputs to all gates.the operation of these gates is divided into 2 phases. The phases are precharge & evaluation. In the precharge phase gate outputs are charged to high level voltage because PMOS transistors are controlled by clock input which in this phase is low.in the evaluate phase, the outputs of the gate can conditionally change to low voltage level. The logic of the gate is implemented only with NMOS transistors those transistors dictate if the outputs will be connected to the low voltage level to be discharged or not.here Domino Inverter is implemented in 90 nm technology using Microwind. When clkdata is low,in precharge state Pmos1 conducts output is driven depending on clk data i.e pmos2 conducts so output is charged to Vdd, in evaluate phase clock1 is high so nmos2 conducts & nmos1 doesn t conduct so out1 retains the charge. When clkdata is high nmos1 conducts,in precharge phase pmos1 conducts, so output is reduced as it discharges since pmos2 is off & in evaluate phase nmos2 conducts so output is pulled down to 0.The schematic diagram is shown in fig 2.Vdd Supply of 1.2 volt is given, input sequence is 01010. C ox = gate oxide capacitance, (W/L) = width to length ratio of the leaking MOS transistor., μ 0 = zero bias mobility, Vgs = gate to source voltage, V T = thermal voltage which is about 26mV at temperature T= 300K and n is the subthreshold swing coefficient given by 1 +(C d/c ox) where C d is the depletion layer capacitance of the source/drain junction. The equation (1) says that the leakage current is exponentially proportional to (Vgs -Vth), Which implies leakage can be reduced by increasing Vth or reducing Vgs. Domino logic is one of the effective circuit configurations for implementing high speed logic designs. Domino circuits provide the advantages of faster transition and glitch-free operation. Figure -1: A Domino Logic inverter Circuit 2018, IRJET Impact Factor value: 7.211 ISO 9001:2008 Certified Journal Page 888

2. SELF CONTROLLABLE VOLTAGE LEVEL SVL stands for Self controllable Voltage Level. Self controllable voltage level (SVL) is technique for leakage reduction within the device. SVL is a technique which can be set either at the top of the load circuit, or bottom of the load. Upper self controllable voltage level (USVL) technique is applied to reduce the supply voltage and Lower self controllable voltage level (LSVL) system is utilized to boost up the ground node voltage. 2.1 LOWER SELF CONTROLLABLE VOLTAGE LEVEL (LSVL) An LSVL circuit in general, consists of a single NMOS switch and m weakly connected nmos switches connected in series which increases the source voltage appearing across the load circuit in active mode. Here m=2 is considered. A negative control signal (clk2) turns on pmos_3 & pmos_2 and turns off nmos_1. so that VS is supplied to the stand-by inverter through 2 p-sws.the on-nmos switch connects the load circuit and Vss in the sleep mode on request whereas the weakly-on PMOS transistors connect the load circuit and Vss in the active mode. Source voltage (VS) is increased by mv, so the substrate bias (i.e., back-gate bias) (Vsub), expressed by Vsub = mv ----(2) Vs=Vss+2v ----(3) Figure -3:Lower Self controllable Voltage Level Circuit with static cmos inverter as load 2.2 UPPER SELF CONTROLLABLE VOLTAGE LEVEL Figure -2:Lower Self controllable Voltage Level Circuit Figure- 4: Upper Self controllable Voltage level 2018, IRJET Impact Factor value: 7.211 ISO 9001:2008 Certified Journal Page 889

2.3 LOWER SELF VOLTAGE LEVEL CIRCUIT WITH DOMINO INVERTER AS LOAD Figure-5: Upper Self controllable Voltage level with static cmos inverter as load An USVL circuit, in general, consists of a single PMOS switch and m weakly connected nmos switches connected in series.here m=2 is considered. When gate voltage of standby inverter is 0,pmos2-2 is turned on & nmos3_1 is turned off. When clockavl turns on nmos1_5, nmos2_4 & turns off pmos1_3, Vdd is supplied to inverter through 2 nmos. Figure -6: Lower Adaptive Voltage Level Circuit with Domino Inverter as load Now, the drain volltage of off nmos is Vdsn = Vdc 2v -----(4) v is voltage drop in single nmos.hence, Vdsn is reduced which in turn increases the barrier height of the off-nmos. Therefore Drain Induced Barrier Lowering (DIBL) effect is reduced and therefore the threshold voltage of the nmos transistor is increased. This results in a decrease in subthreshold leakage current of the nmos transistor in the load circuit. Figure -7: Voltage waveforms & power consumption Lower Adaptive Voltage Level Circuit with Domino Inverter as load 2018, IRJET Impact Factor value: 7.211 ISO 9001:2008 Certified Journal Page 890

Figure -8: Power dissipation of Lower Adaptive Voltage Level Circuit with Domino Inverter as load 2.4 UPPER ADAPTIVE VOLTAGE LEVEL CIRCUIT WITH DOMINO INVERTER AS LOAD Figure -11: Power dissipation of Upper Adaptive Voltage Level Circuit with Domino Inverter as load TABLE-1: SIMULATION RESULTS 3. CONCLUSION Figure -9: Upper Adaptive Voltage Level Circuit with Domino Inverter as load The simulation results reveal that Upper SVL with Domino inverter has less power consumption of 25.167 μw which is 35.88 % less than Static CMOS inverter.power Dissipation is 0.025mW in Upper SVL with Domino inverter which is 35% less than Static CMOS inverter. Propagation Delay is also less i.e 700 ps.domino inverter with USVL is better in performance than with LSVL. So it can be concluded that USVL is better choice. Figure -10: Voltage waveforms & power consumption Upper Adaptive Voltage Level Circuit with Domino Inverter as load REFERENCES [1] Pushpa Saini,Rajesh Mehra Leakage Power Reduction in CMOS VLSI Circuits, International Journal of Computer Applications (0975 8887) Volume 55 No.8, October 2012. [2] Rita Fariya,T.Sai Baba, D.Lakshmaiah, Deign of Low power Domino Logic Circuits, International Journal of Technology and Engineering Science [IJTES]TM Volume 3[12], pp: 5156-5160, December 2015 [3] Ms.Amrita Pahadia #1, Dr. Uma Rathore Bhatt Layout Design, Analysis and Implementation of Combinational and 2018, IRJET Impact Factor value: 7.211 ISO 9001:2008 Certified Journal Page 891

Sequential Circuits using Microwind, SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) volume 2 Issue 2 May to Aug 2015 [4] Ankita Sharma, Divyanshu Rao, Ravi Mohan, Design and Implementation of Domino Logic Circuit in CMOS Journal of Network Communications and Emerging Technologies (JNCET) www.jncet.org Volume 6, Issue 12, December (2016) [5] Pushpa Raikwal, V. Neema, S. Katiyal LOW POWER WITH IMPROVED NOISE MARGIN FOR DOMINO CMOS NAND GATE International Journal Of Computational Engineering Research / ISSN: 2250 3005 [6] Domino Logic Circuit with Reduced Leakage and Improved Noise Margin, H. Mangalam* and K. Gunavathi,International Journal of Applied Engineering Research ISSN 0973-4562 Volume 2, Number 4 (2007), pp. 585 593 [7] K. Kalai Selvi, Enhancement of Back Gate Bias to Reduce Power Dissipation in Domino Inverter by Lower Adaptive Voltage Level Circuit,Journal of Network Communications and Emerging Technologies (JNCET) Volume 8, Issue 10, October (2018) BIOGRAPHY K. Kalai Selvi completed M.E in Optical Communication at Alagappa Chettiar College of Engineering & Technology, Anna University. Working as Assistant Professor in Government College of Engineering,Tirunelveli, Tamil Nadu. Has 12 years of teaching experience. 2018, IRJET Impact Factor value: 7.211 ISO 9001:2008 Certified Journal Page 892

2024 © hobbydocbox.com Privacy Policy | Terms of Service | Feedback