Lecture 27 ANNOUNCEMENTS Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website Final Exam Review Session: Friday 12/14, 3PM, HP Auditorium Video will be posted online by Monday 12/17 Final Exam: Thursday 12/20, 12:30PM 3:30PM, 277 Cory Closed book; 6 pages of notes only Comprehensive in coverage: Material of MT#1 and MT#2, plus MOSFET amplifiers, MOSFET current sources, BJT and MOSFET differential amplifiers, feedback. Qualitative questions on state of the art device technology EE105 Fall 2007 Lecture 27, Slide 1 Prof. Liu, UC Berkeley
Outline IC technology advancement Q: How did we get here? Modern BJT technology Q: What is an HBT? Modern MOSFET technology Q: What are the challenges (and potential solutions) for continued MOSFET scaling? EE105 Fall 2007 Lecture 27, Slide 2 Prof. Liu, UC Berkeley
The IC Market The semiconductor industry is approaching $300B/yr in sales Military 2% Communications 24% Computers 42% Industrial 8% Transportation 8% Consumer Electronics 16% EE105 Fall 2007 Lecture 27, Slide 3 Prof. Liu, UC Berkeley Courtesy of r. Bill Flounders, UC Berkeley Microlab
IC Technology Advancement Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor Investment Transistor Scaling SMIC s Fab 4 (Beijing, China) Photo by L.R. Huang, igitimes Better Performance/Cost m) LENGTH (n 100 Market Growth PITCH 10 International Technology Roadmap for Semiconductors YEAR: 2004 2007 2010 2013 2016 HALF-PITCH: 90nm 65nm 45nm 32nm 22nm GATE LOW POWER HIGH PERFORMANCE 1 2000 2005 2010 2015 2020 YEAR EE105 Fall 2007 Lecture 27, Slide 4 Prof. Liu, UC Berkeley
The Nanometer Size Scale MOSFET Carbon nanotube EE105 Fall 2007 Lecture 27, Slide 5 Prof. Liu, UC Berkeley
Nanogap NA etector Prof. Luke Lee, BioEngineering gept. http://www-biopoems.berkeley.edu/ Single-stranded NA ouble-stranded NA Polysilicon Poly-Si Poly-Si Poly-Si Poly-Si Insulator (Si 3 N 4 ) Insulator (Si 3 N 4 ) EE105 Fall 2007 Lecture 27, Slide 6 Prof. Liu, UC Berkeley
IC Fabrication Goal: Mass fabrication (i.e. simultaneous fabrication) of many IC chips on each wafer, each containing millions or billions of transistors Approach: Form thin films of semiconductors, metals, and insulators over an entire wafer, and pattern each layer with a process much like printing (lithography). Planar processing consists of a sequence of additive and subtractive steps with lateral patterning oxidation deposition ion implantation etching lithography EE105 Fall 2007 Lecture 27, Slide 7 Prof. Liu, UC Berkeley
Planar Processing (patented by Fairchild Semiconductor in 1959: J. A. Hoerni, US Patent 3,064,167) EPOSITION of a thin film LITHOGRAPHY Coat with a protective layer Selectively expose the protective layer evelop the protective layer ETCH to selectively remove the thin film Strip (etch) the protective layer EE105 Fall 2007 Lecture 27, Slide 8 Prof. Liu, UC Berkeley Courtesy of r. Bill Flounders, UC Berkeley Microlab
Overview of IC Process Steps Test Bare Silicon Wafer Epitaxy Processed Wafer Anneal eposition/growth Ion Implantation CMP Mask Pattern Generation C SEM Metrology efect etection Etch Lithography EE105 Fall 2007 Lecture 27, Slide 9 Prof. Liu, UC Berkeley Courtesy of r. Bill Flounders, UC Berkeley Microlab
Modern BJT Structure B E C P+polySi eep trench N+polySi p + p + P base N collector P+polySi N + subcollector Shallow trench N + eep trench Features: P substrate Narrow base n+ poly Si emitter Slf Self aligned li p+ poly Si base contacts t Lightly doped collector Heavily doped epitaxial subcollector Shallow trenches and deep trenches filled with SiO 2 for electrical isolation EE105 Fall 2007 Lecture 27, Slide 10 Prof. Liu, UC Berkeley
BJT Performance Parameters Common emitter current gain, β : A 2 B B ie E E E ib B ie E E B B ib B E B C W N n W N n n qa W N n qa I I 2 2 2 2 = = β The cutoff frequency, f T, is the frequency at which β falls to 1. E E i W N It is correlated with the maximum frequency of oscillation, f max. Intrinsic gain T A C A T C o m V V I V V I r g = EE105 Fall 2007 Lecture 27, Slide 11 Prof. Liu, UC Berkeley
Heterojunction Bipolar Transistor (HBT) To improve β, we can increase n ib by using a base material (Si 1 x Ge x ) that has a smaller band gap energy for x = 0.2, E g of Si 1 x Ge x is 0.1eV smaller than for Si n 2 i β = E g exp kt B n 2 ib E n 2 ie N N E B W W E B Note that this allows a large β to be achieved with large N B (even >N E ), which is advantageous for increasing Early voltage (V A ) reducing base resistance EE105 Fall 2007 Lecture 27, Slide 12 Prof. Liu, UC Berkeley
Modern MOSFET Structures (Intel Penryn, from www.semiconductor.com) com) N-channel MOSFETs P-channel MOSFETs 45nm CMOS technology features: High permittivity gate dielectric and metal gate electrodes strained channel regions shallow trench isolation EE105 Fall 2007 Lecture 27, Slide 13 Prof. Liu, UC Berkeley
MOSFET Performance Parameters Transconductance (short channel MOSFET): I gm = vwcox = V V GS TH The average carrier velocity v isdependent on the velocity at which carriers are injected from the source into the channel, which is dependent on the carrier mobility The cutoff frequency of a MOSFET is given by 2πf = T g C m GS Intrinsic gain: I 1 1 g mro = = V V λ I λ ( V VTH ) GS TH GS EE105 Fall 2007 Lecture 27, Slide 14 Prof. Liu, UC Berkeley
MOSFET Scaling Challenges Suppression of short channel effects Gain in I ON is incommensurate withl L g scaling Variability in performance Sub wavelength lithography: (Costly resolution enhancement techniques are needed) Random variations: Photoresist line edge edge roughness photoresist esign Mask Wafer 250nm SiO 2 MOSFET: Source Substrate 180nm OPC Gate L g Gate L eff X j rain N sub 90nm and Below PSM 0 180 OPC T ox 0 180 Statistical dopant fluctuations A. Asenov, Source Symp. VLSI Tech. ig., pp. rain 86-87, 2007. A. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002 EE105 Fall 2007 Lecture 27, Slide 15 Prof. Liu, UC Berkeley
V TH Roll Off V TH decreases with L g Effect is exacerbated by high values of V S M. Okuno et al., 2005 IEM p. 52 Qualitative explanation: The source & drain p n junctions assist in depleting the Si underneath the gate. The smaller the L g, the greater the percentage of charge balanced by the S/ p n junctions: n+ V G p n+ x j depletion region Large L g : S Small L g : S EE105 Fall 2007 Lecture 27, Slide 16 Prof. Liu, UC Berkeley
Why New Transistor Structures? Leakage must be suppressed in order to reduce L g Note that V TH reduction due to IBL, the root cause for λ > 0, is also TH the cause for increased MOSFET leakage (I >0 for V GS = 0V) with MOSFET miniaturization Leakage occurs in region far from channel surface Let s get rid of it! L g Thin-Body MOSFET Gate Gate Source rain Silicon-on- Buried Oxide Insulator (SOI) Substrate Wafer EE105 Fall 2007 Lecture 27, Slide 17 Prof. Liu, UC Berkeley
Thin Body MOSFETs Leakage is suppressed by using a thin body (T Si < L g ) Channel doping is not needed dd higher h carrier mobility ouble gate structure is more scalable (to L g <10nm) Ultra-Thin Body (UTB) L L g ouble-gate (G) Gate Gate Source rain T Si Source rain T Si Gate Buried Oxide Substrate EE105 Fall 2007 Lecture 27, Slide 18 Prof. Liu, UC Berkeley
ouble Gate FinFET Planar G-FET FinFET L g L g Gate rain T Si Source Gate Gate rain Fin Height H FIN = W/2 Source. Hisamoto et al. (UC Berkeley), IEM Technical igest, pp. 1032-1034, 1998 N. Lindert et al. (UC Berkeley), IEEE Electron evice Letters, pp. 487-489, 489 2001 Fin Width = T Si 15nm L g FinFET: GATE 20 nm 10 nm RAIN Y.-K. Choi et al. (UC Berkeley), IEM Technical igest, pp. 421-424, 2001 SOURCE EE105 Fall 2007 Lecture 27, Slide 19 Prof. Liu, UC Berkeley
15 nm L g FinFETs Y.-K. Choi et al. (UC Berkeley), IEM Technical igest, pp. 421-424, 424 2001 T Si = 10 nm; T ox = 2.1 nm rain Curren nt, I d [A/u um] Transfer Characteristics 10-2 10-2 V P+Si 0.4 Ge =-1.0 V 0.6 V d =1.0 V d Gate 10-4 10-6 10-8 10-10 V d =-0.05 V N-body= 2x10 18 cm -3 PMOS V d =0.05 V NMOS 10-4 10-6 10-8 10-10 10-12 10-12 -1.0-0.5 0.0 0.5 1.0 1.5 2.0 Gate Voltage, V g [V] t, I d [ua/ /um] Curren rain Output Characteristics 600 600 V =1 NMOS 500 PMOS V g -V t =1.2V 500 400 Voltage step 400 300 :0.2V 300 200 200 100 100 0 0-1.5-1.0-0.5 0.0 0.5 1.0 1.5 rain Voltage, V d [V] EE105 Fall 2007 Lecture 27, Slide 20 Prof. Liu, UC Berkeley
10 nm L g FinFETs B. Yu et al. (AM & UC Berkeley), IEM Technical igest, pp. 251-254, 254 2002 Gate rain Source Poly-Si NiSi 220Å SiO2 cap Si Fin BOX Lg=10nm EE105 Fall 2007 Lecture 27, Slide 21 Prof. Liu, UC Berkeley
MOSFET Scaling Scenario Advanced structures will enable Si MOSFET scaling to L g <10 nm metallic gate high-κ gate dielectric L g (nm): 50 40 30 20 10 S G Si strained Si classic al forward body biasing multi-gate S G Si G EE105 Fall 2007 Lecture 27, Slide 22 Prof. Liu, UC Berkeley
The End is Not the Limit! Innovations in process technology, materials, and device design will sustain the Si revolution R SA ALES($)/Y Mainframes (>1 persons per computer) PCs (1 person/computer) UbiComp (>1 computers per person) Acknowledgement: Mark Weiser TIME Sensatex today Investment Technology, evice & Circuit Innovations, Heterogeneous Integration Market Growth Lower Power, Lower Cost Information technology will for better quality-of-life pervasive embedded human-centered solving societalscale problems Energy Health care Environment isaster response Philips Transportation EE105 Fall 2007 Lecture 27, Slide 23 Prof. Liu, UC Berkeley
EECS 105 in the Grand Scheme Example electronic system: cell phone EE105 Fall 2007 Lecture 27, Slide 24 Prof. Liu, UC Berkeley