Automotive grade N-channel 500 V, 0.23 Ω, 17 A, Zener-protected SuperMESH Power MOSFET in a D 2 PAK package. Features

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Transcription:

Automotive grade N-channel 500 V, 0.23 Ω, 17 A, Zener-protected SuperMESH Power MOSFET in a D 2 PAK package Features Datasheet - production data TAB 3 1 D²PAK Figure 1. Internal schematic diagram D(2) Order code V DS R DS(on) max I D P W STB21NK50Z 500 V 0.27 Ω 17 A 190 W Designed for automotive applications and AEC-Q101 qualified Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeatability Applications Switching applications Description G(1) S(3) AM16160v1 This device is an N-channel Zener-protected Power MOSFET developed using STMicroelectronics' SuperMESH technology, achieved through optimization of ST's well established strip-based PowerMESH layout. In addition to a significant reduction in onresistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. Table 1. Device summary Order code Marking Packages Packaging STB21NK50Z 21NK50Z D²PAK Tape and reel September 2014 DocID15026 Rev 2 1/15 This is information on a product in full production. www.st.com

Contents STB21NK50Z Contents 1 Electrical ratings............................................ 3 2 Electrical characteristics..................................... 4 2.1 Electrical characteristics (curves)............................. 6 3 Test circuits.............................................. 8 4 Package mechanical data..................................... 9 5 Packaging mechanical data.................................. 11 6 Revision history........................................... 13 2/15 DocID15026 Rev 2

Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V DS Drain-source voltage (V GS = 0) 500 V V GS Gate-source voltage ± 30 V I D Drain current (continuous) at T C = 25 C 17 A I D Drain current (continuous) at T C =100 C 10.71 A (1) I DM Drain current (pulsed) 68 A P TOT Total dissipation at T C = 25 C 190 W Derating Factor 1.51 W/ C Vesd(G-S) G-S ESD (HBM C=100 pf, R=1.5 kω) 6000 V dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns T stg Storage temperature -55 to 150 C T J Max operating junction temperature 150 C 1. Pulse width limited by safe operating area 2. I SD 17 A, di/dt 200 A/µs,V DD V (BR)DSS, T J T JMAX Table 3. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 0.66 C/W R thj-amb Thermal resistance junction-ambient max 62.5 C/W T l Maximum lead temperature for soldering purpose 300 C Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not-repetitive (pulse width limited by T j max ) Single pulse avalanche energy (starting T J =25 C, I D =I AR, V DD =50 V) 17 A 850 mj DocID15026 Rev 2 3/15 15

Electrical characteristics STB21NK50Z 2 Electrical characteristics (T CASE = 25 C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-source breakdown voltage Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) I D = 1mA, V GS = 0 500 V V DS = 500 V 1 µa V DS = 500 V, T C =125 C 50 µa V GS = ±20 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 100 µa 3 3.75 4.5 V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 8.5 A 0.23 0.27 Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance - 2600 pf C oss Output capacitance V DS = 25 V, f=1 MHz, V GS =0-328 pf C rss Reverse transfer capacitance - 72 pf (1) Equivalent output C oss eq. capacitance V GS =0, V DS =0 to 400 V - 187 pf Q g Total gate charge V DD =400 V, I D = 17 A - 85 119 nc Q gs Gate-source charge V GS =10 V - 15.5 nc Q gd Gate-drain charge (see Figure 15) - 42 nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS 4/15 DocID15026 Rev 2

Electrical characteristics Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 250 V, I D = 8.5 A, - 28 - ns t r Rise time R G = 4.7Ω, V GS = 10 V (see Figure 16) - 20 - ns t d(off) Turn-off delay time V DD = 250 V, I D = 8.5 A, - 70 - ns t f Fall time R G = 4.7 Ω, V GS =10 V (see Figure 16) - 15 - ns Table 8. Gate-source Zener diode Symbol Parameter Test conditions Min Typ. Max. Unit V (BR)GSO Gate-source breakdown voltage I GS = ± 1mA, I D =0 30 - - V The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and cost-effective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. Table 9. Source drain diode Symbol Parameter Test conditions Min Typ. Max Unit I SD Source-drain current - 17 A I SDM (1) V SD (2) Source-drain current (pulsed) - 68 A Forward on voltage I SD = 17 A, V GS =0-1.6 V t rr Reverse recovery time I SD = 17 A, - 355 ns Q rr Reverse recovery charge di/dt = 100 A/µs, V R = 100 V - 3.90 µc I RRM Reverse recovery current (see Figure 16) - 22 A t rr Reverse recovery time I SD = 17 A, - 440 ns Q rr Reverse recovery charge di/dt = 100 A/µs, V R = 100 V, Tj=150 C - 5.72 µc I RRM Reverse recovery current (see Figure 16) - 25 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% DocID15026 Rev 2 5/15 15

Electrical characteristics STB21NK50Z 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized B VDSS vs temperature Figure 7. Static drain-source on-resistance 6/15 DocID15026 Rev 2

Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on-resistance vs temperature Figure 12. Source-drain diode forward characteristics Figure 13. Maximum avalanche energy vs temperature DocID15026 Rev 2 7/15 15

Test circuits STB21NK50Z 3 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD VGS VD RG RL D.U.T. 2200 μf 3.3 μf VDD Vi=20V=VGMAX 2200 μf 12V IG=CONST 2.7kΩ 47kΩ 100Ω 100nF D.U.T. 1kΩ VG PW 47kΩ PW 1kΩ AM01468v1 AM01469v1 Figure 16. Test circuit for inductive load switching and diode recovery times Figure 17. Unclamped inductive load test circuit G 25 Ω D S A D.U.T. B A FAST DIODE B A B D L=100μH 3.3 1000 μf μf VDD VD ID L 2200 μf 3.3 μf VDD G RG S Vi D.U.T. AM01470v1 Pw AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf ID IDM 0 90% 10% VDS 10% 90% VDD VDD VGS 90% AM01472v1 0 10% AM01473v1 8/15 DocID15026 Rev 2

Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 20. D²PAK (TO-263) drawing 0079457_T DocID15026 Rev 2 9/15 15

Package mechanical data STB21NK50Z Table 10. D²PAK (TO-263) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0 8 10/15 DocID15026 Rev 2

Package mechanical data Figure 21. D²PAK footprint (a) 16.90 12.20 5.08 1.60 9.75 3.50 Footprint a. All dimension are in millimeters DocID15026 Rev 2 11/15 15

Packaging mechanical data STB21NK50Z 5 Packaging mechanical data Figure 22. Tape 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 12/15 DocID15026 Rev 2

Packaging mechanical data REEL DIMENSIONS Figure 23. Reel 40mm min. T Access hole At slot location D B C A N Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Table 11. D²PAK (TO-263) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A0 10.5 10.7 A 330 B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 13.2 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 26.4 F 11.4 11.6 N 100 K0 4.8 5.0 T 30.4 P0 3.9 4.1 P1 11.9 12.1 Base qty 1000 P2 1.9 2.1 Bulk qty 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID15026 Rev 2 13/15 15

Revision history STB21NK50Z 6 Revision history Table 12. Document revision history Date Revision Changes 16-Sep-2008 1 First issue 19-Sep-2014 2 Updated: title and features in cover page Updated: Section 4: Package mechanical data and Section 5: Packaging mechanical data Minor text changes 14/15 DocID15026 Rev 2

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2014 STMicroelectronics All rights reserved DocID15026 Rev 2 15/15 15