Power MOSFET PRODUCT SUMMARY (V) 450 R DS(on) (Ω) = 0.63 Q g (Max.) (nc) 80 Q gs (nc) 1 Q gd (nc) 41 Configuration Single TO0 D G G D S S NChannel MOSFET ORDERING INFORMATION Package Lead (Pb)free SnPb FEATURES Dynamic dv/dt Rating Repetitive Avalanche Rated Fast Switching Ease of Paralleling Simple Drive Requirements Lead (Pb)free Available Available RoHS* COMPLIANT DESCRIPTION Third generation Power MOSFETs from Vishay provides the designer with the best combination of fast switching, ruggedized device design, low onresistance and cost effectiveness. The TO0 package is universally preferred for all commercialindustrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO0 contribute to its wide acceptance throughout the industry. TO0 IRF744PbF SiHF744E3 IRF744 SiHF744 ABSOLUTE MAXIMUM RATINGS T C = 5 C, unless otherwise noted PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 450 GateSource Voltage ± 0 V Continuous Drain Current at T C = 5 C 8.8 T C = 100 C 5.6 A Pulsed Drain Current a M 35 Linear Derating Factor 1.0 W/ C Single Pulse Avalanche Energy b E AS 540 mj Repetitive Avalanche Current a I AR 8.8 A Repetitive Avalanche Energy a E AR 13 mj Maximum Power Dissipation T C = 5 C P D 15 W Peak Diode Recovery dv/dt c dv/dt 3.5 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 150 Soldering Recommendations (Peak Temperature) for 10 s 300 d C Mounting Torque 63 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 50 V, starting T J = 5 C, L = 1 mh, R G = 5 Ω I AS = 8.8 A (see fig. 1). c. I SD 8.8 A, dv/dt 00 A/µs, V DD, T J 150 C. d. 1.6 mm from case. 10 lbf in 1.1 N m * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91056 S8309Rev. A, 19Jan09 1
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 6 CasetoSink, Flat, Greased Surface R thcs 0.50 C/W Maximum JunctiontoCase (Drain) R thjc 1.0 SPECIFICATIONS T J = 5 C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = 0 V, = 50 µa 450 V Temperature Coefficient Δ /T J Reference to 5 C, = 1 ma 0.59 V/ C GateSource Threshold Voltage (th) =, = 50 µa.0 4.0 V GateSource Leakage I GSS = ± 0 ± 100 na = 450 V, = 0 V 5 Zero Gate Voltage Drain Current SS = 360 V, = 0 V, T J = 15 C 50 µa DrainSource OnState Resistance R DS(on) = = 5.3 A b 0.63 Ω Forward Transconductance g fs = 50 V, = 5.3 A b 4.5 S Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance C iss C oss C rss = 0 V = 5 V f = 1.0 MHz, see fig. 5 1400 370 140 Total Gate Charge Q g 80 = 8.8 A, = 360 V, GateSource Charge Q gs = 1 see fig. 6 and 13 b GateDrain Charge Q gd 41 TurnOn Delay Time t d(on) 8.7 Rise Time t r V DD = 5 V, = 8.8 A 8 TurnOff Delay Time t d(off) R G = 9.1 Ω, R D = 5 Ω, see fig. 10 b 58 Fall Time t f 7 Between lead, Internal Drain Inductance L D 6 mm (0.5") from 4.5 D package and center of G Internal Source Inductance L S die contact 7.5 S pf nc ns nh DrainSource Body Diode Characteristics MOSFET symbol Continuous SourceDrain Diode Current I S showing the 8.8 D integral reverse G Pulsed Diode Forward Current a I SM p n junction diode 35 S A Body Diode Voltage V SD T J = 5 C, I S = 8.8 A, = 0 V b.0 V Body Diode Reverse Recovery Time t rr T J = 5 C, I F = 8.8 A, di/dt = 100 A/µs b 490 740 ns Body Diode Reverse Recovery Charge Q rr 3. 4.8 µc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 µs; duty cycle %. Document Number: 91056 S8309Rev. A, 19Jan09
TYPICAL CHARACTERISTICS 5 C, unless otherwise noted, Drain Current (A) 10 1 Top Bottom 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 4.5 V, Drain Current (A) 10 1 150 C 5 C 91056_01 0 µs Pulse Width T C = 5 C 10 0 10 0 10 1, DraintoSource Voltage (V) 91056_03 10 0 4 0 µs Pulse Width = 50 V 5 6 7 8 9 10, GatetoSource Voltage (V) Fig. 1 Typical Output Characteristics, T C = 5 C Fig. 3 Typical Transfer Characteristics, Drain Current (A) 91056_0 10 1 Top Bottom 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 10 0 10 0 10 1 0 µs Pulse Width T C = 150 C, DraintoSource Voltage (V) 4.5 V R DS(on), DraintoSource On Resistance (Normalized) 91056_04 3.5 3.0.5.0 1.5 1.0 0.5 = 8.8 A = 0.0 60 40 0 0 0 40 60 80 100 10 140 160 T J, Junction Temperature ( C) Fig. Typical Output Characteristics, T C = 150 C Fig. 4 Normalized OnResistance vs. Temperature Document Number: 91056 S8309Rev. A, 19Jan09 3
Capacitance (pf) 91056_05 3000 500 000 1500 1000 500 0 10 0 10 1 = 0 V, f = 1 MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss C oss C rss, DraintoSource Voltage (V) I SD, Reverse Drain Current (A) 91056_07 10 1 150 C 5 C 10 0 = 0 V 0.4 0.6 0.8 1.0 1. 1.4 1.6 10 1 V SD, SourcetoDrain Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage Fig. 7 Typical SourceDrain Diode Forward Voltage, GatetoSource Voltage (V) 91056_06 0 16 1 8 4 0 = 8.8 A = 90 V = 5 V = 360 V 0 0 40 60 80 Q G, Total Gate Charge (nc) For test circuit see figure 13, Drain Current (A) 91056_08 10 3 5 10 5 10 5 1 5 0.1 5 1 10 Operation in this area limited by R DS(on) T C = 5 C T J = 150 C Single Pulse 5, DraintoSource Voltage (V) 10 µs 100 µs 1 ms 10 ms 10 5 10 3 Fig. 6 Typical Gate Charge vs. GatetoSource Voltage Fig. 8 Maximum Safe Operating Area Document Number: 91056 4 S8309Rev. A, 19Jan09
R D D.U.T. 10 R G V DD, Drain Current (A) 8 6 4 Pulse width 1 µs Duty factor 0.1 % Fig. 10a Switching Time Test Circuit 90 % 91056_09 0 5 50 75 100 15 150 T C, Case Temperature ( C) 10 % t d(on) t r t d(off) t f Fig. 9 Maximum Drain Current vs. Case Temperature Fig. 10b Switching Time Waveforms 10 Thermal Response (Z thjc ) 1 0.1 D = 0.5 0. 0.1 0.05 0.0 0.01 Single Pulse (Thermal Response) 10 10 5 10 4 10 3 10 0.1 1 10 P DM t 1 t Notes: 1. Duty Factor, D = t 1 /t. Peak T j = P DM x Z thjc T C 91056_11 t 1, Rectangular Pulse Duration (s) Fig. 11 Maximum Effective Transient Thermal Impedance, JunctiontoCase Vary t p to obtain required I AS L t p V DD R G I AS D.U.T V DD t p 0.01 Ω I AS Fig. 1a Unclamped Inductive Test Circuit Fig. 1b Unclamped Inductive Waveforms Document Number: 91056 S8309Rev. A, 19Jan09 5
E AS, Single Pulse Energy (mj) 91056_1c 100 1000 800 600 400 00 Top Bottom V 0 DD = 50 V 5 50 75 100 15 150 Starting T J, Junction Temperature ( C) 3.9 A 5.6 A 8.8 A Fig. 1c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q G 1 V 0. µf 50 kω 0.3 µf Q GS Q GD D.U.T. V DS V G 3 ma Charge Fig. 13a Basic Gate Charge Waveform Fig. 13b Gate Charge Test Circuit I G Current sampling resistors Document Number: 91056 6 S8309Rev. A, 19Jan09
Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = * D.U.T. I SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD * = 5 V for logic level devices Fig. 14 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?91056. Document Number: 91056 S8309Rev. A, 19Jan09 7
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