December 21, 2004 Motorola MPXV5004G Integrated Pressure Sensor Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Table of Contents Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 3 Process Analysis 3.0 Process Overview 3.1 Die Edge 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Contacts 3.6 Bipolar Transistors 3.7 Passive Components 4 Sensor Analysis 4.1 Piezoresistive Sensor Overview 4.2 Bulk Machined Cavity Cross-Sectional Analysis 4.3 Implanted Piezoresistors 5 Materials Analysis 5.1 SEM EDS Analysis Of Metals 5.2 SRP Anaylsis of the Substrate 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Side 2.1.3 Package Bottom 2.1.4 Top View X-Ray 2.1.5 Side View X-Ray 2.1.6 Cross-Sectional Diagram from Data Sheet 2.1.7 Cavity Photograph 2.1.8 Die Photograph MPXV5004G 2.1.9 Die Markings 2.1.10 Die Markings 3 Process Analysis 3.1.1 Die Edge Cross-Sectional View 3.1.2 Detail of Die Edge Cross-Sectional View 3.2.1 Typical Bond Pad 3.2.2 Bond Pad Structure 3.2.3 Detail of Bond Pad Structure 3.2.4 Opened Passivation Window 3.2.5 Bond Pad Contact to Substrate 3.3.1 Dielectric Stack 3.4.1 Minimum Pitch Metal 3.4.2 Metal Profile 3.6.1 Vertical NPN Transistor Plan-View 3.6.2 Vertical NPN Transistor Silicon Delineation 3.6.3 Vertical NPN Transistor SCM Scan 3.6.4 Vertical NPN Transistor SEM View 3.6.5 Vertical NPN Transistor Emitter Contact 3.6.6 Vertical NPN Transistor Base Contact 3.6.7 Ganged Lateral PNP Transistors Plan-View 3.6.8 Ganged Lateral PNP Transistor Silicon Delineation 3.6.9 Ganged Lateral PNP Transistors SCM Scan 3.6.10 Ganged Lateral PNP Transistors SEM View 3.6.11 Lateral PNP Transistor Collector Contact 3.6.12 Lateral PNP Transistor Emitter Contact
Overview 1-2 3.7.1 Metal Film Resistor Plan-View 3.7.2 Metal Film Resistor Cross-Section 3.7.3 MOS Capacitor Plan-View 3.7.4 MOS Capacitor Cross-Section 4 Sensor Analysis 4.1.1 Implanted Piezoresistors 4.2.1 Silicon Substrate Overview 4.2.2 Etched Cavity (Die Surface) 4.2.3 Etched Cavity (Die Backside) 4.2.4 Detail of Oxide/Nitride Mask 4.2.5 Edge of Cavity Silicon Delineation 4.3.1 Cross-Section through Drive/Output Lines 4.3.2 Contacts to Drive/Output Line (P-Well) 4.3.3 SCM of Drive/Output Line (P-Well) 4.3.4 SEM Image of P-Well over Sensor Membrane 4.3.5 SCM Image of P-Well over Sensor Membrane 4.3.6 Piezoresistors Arranged in Wheatstone Bridge Plan-View 4.3.7 Piezoresistor Cross-Section 4.3.8 Piezoresistor SCM Scan 5 Materials Analysis 5.1.1 SEM EDS Spectrum of Metal 5.1.2 SEM EDS Spectrum of Metal Film Resistor 5.2.1 SRP of Substrate 1.2 List of Tables 3.2.1 Bond Pad Horizontal Dimensions 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Vertical NPN Transistor Critical Dimensions
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