Adc. W W/ C T J, T stg 65 to C

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Preferred Device Darlington Complementary Silicon Power Transistors This package is designed for generalpurpose amplifier and low frequency switching applications. Features High DC Current Gain h FE = 3 (Typ) @ I C = 5.0 Adc CollectorEmitter Sustaining Voltage @ ma V CEO(sus) = Vdc (Min) Monolithic Construction with BuiltIn BaseEmitter Shunt Resistors This is a PbFree Device* MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit CollectorEmitter Voltage V CEO Vdc CollectorBase Voltage V CB Vdc EmitterBase Voltage V EB 5.0 Vdc Collector Current Continuous Peak I C 12 Adc Base Current I B Adc Total Power Dissipation @ T C = 25 C Derate above 25 C Operating and Storage Temperature Range THERMAL CHARACTERISTICS P D 1 0.857 W W/ C T J, T stg 65 to + C Characteristic Symbol Max Unit Thermal Resistance, JunctiontoCase R JC 1.17 C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Indicates JEDEC Registered Data. 12 AMPERE COMPLEMENTARY SILICON POWER TRANSISTOR VOLTS, 1 WATTS 2 1 BASE 1 COLLECTOR CASE EMITTER 2 TO4AA (TO3) CASE 7 STYLE 1 MARKING DIAGRAM 2N6052G AYYWW MEX PD, POWER DISSIPATION (WATTS) 160 140 1 80 60 40 0 0 25 75 125 1 175 T C, CASE TEMPERATURE ( C) Figure 1. Power Derating 2N6052 G A YY WW MEX = Device Code = PbFree Package = Location Code = Year = Work Week = Country of Orgin ORDERING INFORMATION Device Package Shipping 2N6052G TO3 (PbFree) Units/Tray Preferred devices are recommended choices for future use and best overall value. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 8 September, 8 Rev. 5 1 Publication Order Number: 2N6052/D

Î ELECTRICAL CHARACTERISTICS (T C = 25 C unless otherwise noted) (Note 2) Characteristic Symbol ÎÎÎ Min ÎÎÎÎ ÎÎÎ Max Unit Î OFF CHARACTERISTICS CollectorEmitter Sustaining Voltage (Note 3) (I C = madc, I B = 0) ÎÎ ÎÎÎÎ ÎÎÎ Vdc V CEO(sus) Collector Cutoff Current (V CE = Vdc, I B = 0) I CEO ÎÎÎ ÎÎÎÎ ÎÎÎ madc Collector Cutoff Current I CEX ÎÎÎ (V CE = Rated V CEO, V BE(off) = 1.5 Vdc) (V CE = Rated V CEO, V BE(off) = 1.5 Vdc, T C ÎÎ = 1 C) ÎÎÎÎ ÎÎÎ madc 5.0 ÎÎÎ Emitter Cutoff Current (V BE = 5.0 Vdc, I C = 0) I EBO ÎÎÎÎ ÎÎÎ madc Î ON CHARACTERISTICS (Note 3) Î DC Current Gain h (I C = 6.0 Adc, V CE = 3.0 Vdc) FE Î (I C = 12 Adc, V CE = 3.0 Vdc) ÎÎ 7 18,000ÎÎÎ Î CollectorEmitter Saturation Voltage V (I C = 6.0 Adc, I B CE(sat) Vdc ÎÎÎ = 24 madc) (I C = 12 Adc, I B = 1 madc) ÎÎ ÎÎÎÎ 3.0 ÎÎÎ BaseEmitter Saturation Voltage (I C = 12 Adc, I B = 1 madc) V BE(sat) ÎÎÎ ÎÎÎÎ 4.0 ÎÎÎ Vdc BaseEmitter On Voltage (I C = 6.0 Adc, V CE = 3.0 Vdc) V BE(on) ÎÎÎ ÎÎÎÎ 2.8 ÎÎÎ Vdc Î DYNAMIC CHARACTERISTICS Magnitude of Common Emitter SmallSignal Short Circuit Forward h fe ÎÎÎ 4.0 ÎÎÎÎ ÎÎÎ MHz Current Transfer Ratio (I C = 5.0 Adc, V CE = 3.0 Vdc, f = MHz) Î Output Capacitance (V CB = Vdc, I E = 0, f = MHz) C ob pf Î SmallSignal Current Gain 2. Indicates JEDEC Registered Data. 3. Pulse test: Pulse Width = s, Duty Cycle = %. (I C = 5.0 Adc, V CE = 3.0 Vdc, f = khz) h fe R B & R C VARIED TO OBTAIN DESIRED CURRENT LEVELS D 1 MUST BE FAST RECOVERY TYPE, eg: 1N5825 USED ABOVE I B ma MSD6 USED BELOW I B ma V 2 approx + 8.0 V 0 V 1 approx - 8.0 V t r, t f ns DUTY CYCLE = % 25 s 51 Figure 2. Switching Times Test Circuit R B D 1 + 4.0 V R C TUT 5.0 k for t d and t r, D 1 is disconnected and V 2 = 0 V CC - 30 V For NPN test circuit reverse diode and voltage polarities. SCOPE t, TIME ( s) μ 5.0 t s t f 3.0 5.0 Figure 3. Switching Times t r t d @ V BE(off) = 0 2N6052 2N6059 V CC = 30 V I C /I B = 2 I B1 = I B2 2

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.7 0.3 0.07 0.03 0.02 D = 0.02 SINGLE PULSE 0.01 R JC (t) = r(t) R JC R JC = 1.17 C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 T J(pk) - T C = P (pk) JC (t) P (pk) t 1 t 2 DUTY CYCLE, D = t 1 /t 2 0.01 0.01 0.02 0.03 0.3 3.0 5.0 30 0 t, TIME (ms) Figure 4. Thermal Response There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C V CE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figures 5, and 6 is based on T J(pk) = C; T C is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to % provided T J(pk) C; T J(pk) may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. IC, COLLECTOR CURRENT (AMP) 5.0 ACTIVEREGION SAFE OPERATING AREA T J = C ms ms 5.0 ms SECOND BREAKDOWN LIMITED BONDING WIRE LIMITED THERMAL LIMITATION @T C = 25 C (SINGLE PULSE) ms 30 70 V CE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 5. d c hfe, SMALL-SIGNAL CURRENT GAIN 0 0 0 30 T C = 25 C V CE = 3.0 V I C = 5.0 A 5.0 0 5.0 f, FREQUENCY (khz) V R, REVERSE VOLTAGE (VOLTS) Figure 6. SmallSignal Current Gain C, CAPACITANCE (pf) 70 C ib C ob Figure 7. Capacitance 3

hfe, DC CURRENT GAIN,000,000 V CE = 3.0 V T J = 1 C 0 0 25 C 0 0-55 C 0.3 3.0 5.0 Figure 8. DC Current Gain VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) 3.0 2.6 2.2 1.8 1.4 I C = 3.0 A 6.0 A 9.0 A 12 A 3.0 5.0 30 I B, BASE CURRENT (ma) Figure 9. Collector Saturation Region V, VOLTAGE (VOLTS) 3.0 2.5 1.5 V BE(sat) @ I C /I B = 2 V BE @ V CE = 3.0 V V CE(sat) @ I C /I B = 2 0.3 3.0 5.0 Figure. On Voltages 4

PACKAGE DIMENSIONS TO4 (TO3) CASE 7 ISSUE Z V H E 2 1 A N U C T SEATING PLANE D 2 PL K 3 (0.005) M T Q M Y M L G Y Q 3 (0.005) M T B Y M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. ALL RULES AND NOTES ASSOCIATED WITH REFERENCED TO-4AA OUTLINE SHALL APPLY. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 1.5 REF 39.37 REF B --- --- 26.67 C 0.335 6.35 8.51 D 0.038 0.043 0.97 9 E 5 0.070 1.40 1.77 G 0.430 BSC.92 BSC H 15 BSC 5.46 BSC K 0.440 0.480 11.18 12.19 L 0.665 BSC 16.89 BSC N --- 0.830 --- 28 Q 51 65 3.84 4.19 U 1.187 BSC 35 BSC V 31 88 3.33 4.77 STYLE 1: PIN 1. BASE 2. EMITTER CASE: COLLECTOR ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 3036752175 or 8003443860 Toll Free USA/Canada Fax: 3036752176 or 8003443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8002829855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 29 Japan Customer Focus Center Phone: 813577338 5 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 2N6052/D